#ifndef __SCU_H__
#define __SCU_H__

#include "main.h"

#define SCU_BASE_ADDR  (0xD0010000)

typedef struct SCU_ {
	volatile uint32_t SW_RST_CONTROL;	 // offset: 0x0 default value: 0x0 read mask: 0xfffff3ff write mask 0xfffff3ff
	volatile uint32_t ACPU_PLL_CTRL_0;	 // offset: 0x4 default value: 0x101025b read mask: 0x3fffffff write mask 0x3fffffff
	volatile uint32_t ACPU_PLL_CTRL_1;	 // offset: 0x8 default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t ACPU_PLL_CTRL_2;	 // offset: 0xC default value: 0x0 read mask: 0x3ffff write mask 0x3ffff
	volatile uint32_t ACPU_PLL_CTRL_3;	 // offset: 0x10 default value: 0x0 read mask: 0xffff write mask 0xffff
	volatile uint32_t ACPU_PLL_CTRL_4;	 // offset: 0x14 default value: 0x1 read mask: 0x1 write mask 0x101
	volatile uint32_t HS_PLL_CTRL_0;	 // offset: 0x18 default value: 0x0 read mask: 0x3fffffff write mask 0x3fffffff
	volatile uint32_t HS_PLL_CTRL_1;	 // offset: 0x1C default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t HS_PLL_CTRL_2;	 // offset: 0x20 default value: 0x0 read mask: 0x3ffff write mask 0x3ffff
	volatile uint32_t HS_PLL_CTRL_3;	 // offset: 0x24 default value: 0x0 read mask: 0xffff write mask 0xffff
	volatile uint32_t HS_PLL_CTRL_4;	 // offset: 0x28 default value: 0x0 read mask: 0x1 write mask 0x101
	volatile uint32_t MEMORY_PLL_CTRL_0;	 // offset: 0x2C default value: 0x0 read mask: 0x3fffffff write mask 0x3fffffff
	volatile uint32_t MEMORY_PLL_CTRL_1;	 // offset: 0x30 default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t MEMORY_PLL_CTRL_2;	 // offset: 0x34 default value: 0x0 read mask: 0x3ffff write mask 0x3ffff
	volatile uint32_t MEMORY_PLL_CTRL_3;	 // offset: 0x38 default value: 0x0 read mask: 0xffff write mask 0xffff
	volatile uint32_t MEMORY_PLL_CTRL_4;	 // offset: 0x3C default value: 0x0 read mask: 0x1 write mask 0x101
	volatile uint32_t MCPU_PLL_CTRL_0;	 // offset: 0x40 default value: 0x10080a7 read mask: 0x3fffffff write mask 0x3fffffff
	volatile uint32_t MCPU_PLL_CTRL_1;	 // offset: 0x44 default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t MCPU_PLL_CTRL_2;	 // offset: 0x48 default value: 0x0 read mask: 0x3ffff write mask 0x3ffff
	volatile uint32_t MCPU_PLL_CTRL_3;	 // offset: 0x4C default value: 0x0 read mask: 0xffff write mask 0xffff
	volatile uint32_t MCPU_PLL_CTRL_4;	 // offset: 0x50 default value: 0x1 read mask: 0x1 write mask 0x101
	volatile uint32_t PERIPH_DIV;	 // offset: 0x54 default value: 0x1 read mask: 0xf write mask 0xf
	volatile uint32_t GATING_CONTROL;	 // offset: 0x58 default value: 0x0 read mask: 0x7 write mask 0x7
	volatile uint32_t BOOTSTRAP_STATUS;	 // offset: 0x5C default value: 0x0 read mask: 0x17f write mask 0x178
	volatile uint32_t ACPU_PLL_STATUS;	 // offset: 0x60 default value: 0x0 read mask: 0x3fffffff write mask 0x0
	volatile uint32_t HS_PLL_STATUS;	 // offset: 0x64 default value: 0x0 read mask: 0x3fffffff write mask 0x0
	volatile uint32_t MEM_PLL_STATUS;	 // offset: 0x68 default value: 0x0 read mask: 0x3fffffff write mask 0x0
	volatile uint32_t MCPU_PLL_STATUS;	 // offset: 0x6C default value: 0x0 read mask: 0x3fffffff write mask 0x0
	volatile uint32_t IRQ_MASK_MAP_CONTROL_0;	 // offset: 0x70 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_1;	 // offset: 0x74 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_2;	 // offset: 0x78 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_3;	 // offset: 0x7C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_4;	 // offset: 0x80 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_5;	 // offset: 0x84 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_6;	 // offset: 0x88 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_7;	 // offset: 0x8C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_8;	 // offset: 0x90 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_9;	 // offset: 0x94 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_10;	 // offset: 0x98 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_11;	 // offset: 0x9C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_12;	 // offset: 0xA0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_13;	 // offset: 0xA4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_14;	 // offset: 0xA8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_15;	 // offset: 0xAC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_16;	 // offset: 0xB0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_17;	 // offset: 0xB4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_18;	 // offset: 0xB8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_19;	 // offset: 0xBC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_20;	 // offset: 0xC0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_21;	 // offset: 0xC4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_22;	 // offset: 0xC8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_23;	 // offset: 0xCC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_24;	 // offset: 0xD0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_25;	 // offset: 0xD4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_26;	 // offset: 0xD8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_27;	 // offset: 0xDC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_28;	 // offset: 0xE0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_29;	 // offset: 0xE4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_30;	 // offset: 0xE8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_31;	 // offset: 0xEC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_32;	 // offset: 0xF0 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_33;	 // offset: 0xF4 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_34;	 // offset: 0xF8 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_35;	 // offset: 0xFC default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_36;	 // offset: 0x100 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_37;	 // offset: 0x104 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_38;	 // offset: 0x108 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_39;	 // offset: 0x10C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_40;	 // offset: 0x110 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_41;	 // offset: 0x114 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_42;	 // offset: 0x118 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_43;	 // offset: 0x11C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_44;	 // offset: 0x120 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_45;	 // offset: 0x124 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_46;	 // offset: 0x128 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_47;	 // offset: 0x12C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_48;	 // offset: 0x130 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_49;	 // offset: 0x134 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_50;	 // offset: 0x138 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_51;	 // offset: 0x13C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_52;	 // offset: 0x140 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_53;	 // offset: 0x144 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_54;	 // offset: 0x148 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_55;	 // offset: 0x14C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_56;	 // offset: 0x150 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_57;	 // offset: 0x154 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_58;	 // offset: 0x158 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_59;	 // offset: 0x15C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_60;	 // offset: 0x160 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_61;	 // offset: 0x164 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_62;	 // offset: 0x168 default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t IRQ_MASK_MAP_CONTROL_63;	 // offset: 0x16C default value: 0x0 read mask: 0x0 write mask 0x30001
	volatile uint32_t AXI_CLK_EN_M0;	 // offset: 0x170 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t AXI_CLK_EN_M1;	 // offset: 0x174 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t AXI_CLK_EN_M2;	 // offset: 0x178 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t AXI_CLK_EN_M3;	 // offset: 0x17C default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t ACPU_PM_STATUS;	 // offset: 0x180 default value: 0x0 read mask: 0xfffff write mask 0x0
	volatile uint32_t BOOT_SSI_XIP_EN;	 // offset: 0x184 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t BOOT_SSI_STATUS;	 // offset: 0x188 default value: 0x0 read mask: 0x3 write mask 0x0
	volatile uint32_t GP_SSI_STATUS;	 // offset: 0x18C default value: 0x0 read mask: 0x3 write mask 0x0
	volatile uint32_t I2C_STATUS;	 // offset: 0x190 default value: 0x0 read mask: 0x1fffff write mask 0x0
	volatile uint32_t WDT_MCPU_SPEED_UP;	 // offset: 0x194 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t GBE0_PWR_CTRL;	 // offset: 0x198 default value: 0x0 read mask: 0x7 write mask 0x7
	volatile uint32_t GBE1_PWR_CTRL;	 // offset: 0x19C default value: 0x0 read mask: 0x7 write mask 0x7
	volatile uint32_t MCPU_L2_SRAM_DEEPSLEEP;	 // offset: 0x1A0 default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t MCPU_L2_SRAM_POWERGATE;	 // offset: 0x1A4 default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t MCPU_HARTID;	 // offset: 0x1A8 default value: 0x0 read mask: 0xffffffff write mask 0xffffffff
	volatile uint32_t MCPU_IO_BASE_ADDR;	 // offset: 0x1AC default value: 0xe0000000 read mask: 0xffffffff write mask 0xffffffff
	volatile uint32_t MCPU_MEM_BASE_ADDR;	 // offset: 0x1B0 default value: 0xf0000000 read mask: 0xffffffff write mask 0xffffffff
	volatile uint32_t MCPU_ICG_DIS;	 // offset: 0x1B4 default value: 0x0 read mask: 0x3 write mask 0x3
	volatile uint32_t MCPU_CLK_DIS;	 // offset: 0x1B8 default value: 0x0 read mask: 0x3 write mask 0x3
	volatile uint32_t MCPU_RST_CORE_PC;	 // offset: 0x1BC default value: 0xd0000000 read mask: 0xffffffff write mask 0x0
	volatile uint32_t DTCM_DEEPSLEEP;	 // offset: 0x1C0 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t DTCM_POWERGATE;	 // offset: 0x1C4 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t ITCM_DEEPSLEEP;	 // offset: 0x1C8 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t ITCM_POWERGATE;	 // offset: 0x1CC default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t MISC_DEEPSLEEP;	 // offset: 0x1D0 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t MISC_POWERGATE;	 // offset: 0x1D4 default value: 0x0 read mask: 0x1 write mask 0x1
	volatile uint32_t JTAG_SEL;	 // offset: 0x1D8 default value: 0x0 read mask: 0xf0003 write mask 0x3
	volatile uint32_t EXT_ADDR;	 // offset: 0x1DC default value: 0x0 read mask: 0xffffff write mask 0xffffff
	volatile uint32_t SW_RST_N_MCPU;	 // offset: 0x1E0 default value: 0x0 read mask: 0x1 write mask 0x1
} SCU_t;

extern SCU_t *const SCU;

/****************************** Bit definition for SW_RST_CONTROL register ********************************/

#define SW_RST_CONTROL_SW_RST_N_WDT_Pos		(0U)
#define SW_RST_CONTROL_SW_RST_N_WDT_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_WDT_Pos)
#define SW_RST_CONTROL_SW_RST_N_WDT    		SW_RST_CONTROL_SW_RST_N_WDT_Msk


#define SW_RST_CONTROL_SW_RST_N_MBOX_Pos		(1U)
#define SW_RST_CONTROL_SW_RST_N_MBOX_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_MBOX_Pos)
#define SW_RST_CONTROL_SW_RST_N_MBOX    		SW_RST_CONTROL_SW_RST_N_MBOX_Msk


#define SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Pos		(2U)
#define SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Pos)
#define SW_RST_CONTROL_SW_RST_N_BOOT_SSI    		SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Msk


#define SW_RST_CONTROL_SW_RST_N_GPSSI_Pos		(3U)
#define SW_RST_CONTROL_SW_RST_N_GPSSI_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_GPSSI_Pos)
#define SW_RST_CONTROL_SW_RST_N_GPSSI    		SW_RST_CONTROL_SW_RST_N_GPSSI_Msk


#define SW_RST_CONTROL_SW_RST_N_I2C_Pos		(4U)
#define SW_RST_CONTROL_SW_RST_N_I2C_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_I2C_Pos)
#define SW_RST_CONTROL_SW_RST_N_I2C    		SW_RST_CONTROL_SW_RST_N_I2C_Msk


#define SW_RST_CONTROL_SW_RST_N_UART_Pos		(5U)
#define SW_RST_CONTROL_SW_RST_N_UART_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_UART_Pos)
#define SW_RST_CONTROL_SW_RST_N_UART    		SW_RST_CONTROL_SW_RST_N_UART_Msk


#define SW_RST_CONTROL_SW_RST_N_USB1_Pos		(6U)
#define SW_RST_CONTROL_SW_RST_N_USB1_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_USB1_Pos)
#define SW_RST_CONTROL_SW_RST_N_USB1    		SW_RST_CONTROL_SW_RST_N_USB1_Msk


#define SW_RST_CONTROL_SW_RST_N_USB0_Pos		(7U)
#define SW_RST_CONTROL_SW_RST_N_USB0_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_USB0_Pos)
#define SW_RST_CONTROL_SW_RST_N_USB0    		SW_RST_CONTROL_SW_RST_N_USB0_Msk


#define SW_RST_CONTROL_SW_RST_N_GMAC_1_Pos		(8U)
#define SW_RST_CONTROL_SW_RST_N_GMAC_1_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_GMAC_1_Pos)
#define SW_RST_CONTROL_SW_RST_N_GMAC_1    		SW_RST_CONTROL_SW_RST_N_GMAC_1_Msk


#define SW_RST_CONTROL_SW_RST_N_GMAC_0_Pos		(9U)
#define SW_RST_CONTROL_SW_RST_N_GMAC_0_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_GMAC_0_Pos)
#define SW_RST_CONTROL_SW_RST_N_GMAC_0    		SW_RST_CONTROL_SW_RST_N_GMAC_0_Msk


#define SW_RST_CONTROL_SW_RST_N_MEN_1_Pos		(12U)
#define SW_RST_CONTROL_SW_RST_N_MEN_1_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_MEN_1_Pos)
#define SW_RST_CONTROL_SW_RST_N_MEN_1    		SW_RST_CONTROL_SW_RST_N_MEN_1_Msk


#define SW_RST_CONTROL_SW_RST_N_MEM_0_Pos		(13U)
#define SW_RST_CONTROL_SW_RST_N_MEM_0_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_MEM_0_Pos)
#define SW_RST_CONTROL_SW_RST_N_MEM_0    		SW_RST_CONTROL_SW_RST_N_MEM_0_Msk


#define SW_RST_CONTROL_SW_RST_N_HS_1_Pos		(14U)
#define SW_RST_CONTROL_SW_RST_N_HS_1_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_HS_1_Pos)
#define SW_RST_CONTROL_SW_RST_N_HS_1    		SW_RST_CONTROL_SW_RST_N_HS_1_Msk


#define SW_RST_CONTROL_SW_RST_N_HS_0_Pos		(15U)
#define SW_RST_CONTROL_SW_RST_N_HS_0_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_HS_0_Pos)
#define SW_RST_CONTROL_SW_RST_N_HS_0    		SW_RST_CONTROL_SW_RST_N_HS_0_Msk


#define SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Pos		(16U)
#define SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Msk		(0x1UL << SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Pos)
#define SW_RST_CONTROL_SW_RST_N_ACPU_BOOT    		SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Msk


#define SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Pos		(17U)
#define SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Msk		(0x7fffUL << SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Pos)
#define SW_RST_CONTROL_SW_RST_N_ACPU_CORE    		SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Msk


/****************************** Bit definition for ACPU_PLL_CTRL_0 register ********************************/

#define ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Pos		(0U)
#define ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Pos)
#define ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN    		ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Msk


#define ACPU_PLL_CTRL_0_ACPU_FOUTEN_Pos		(1U)
#define ACPU_PLL_CTRL_0_ACPU_FOUTEN_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_FOUTEN_Pos)
#define ACPU_PLL_CTRL_0_ACPU_FOUTEN    		ACPU_PLL_CTRL_0_ACPU_FOUTEN_Msk


#define ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Pos		(2U)
#define ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Pos)
#define ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN    		ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Msk


#define ACPU_PLL_CTRL_0_ACPU_FBDIV_Pos		(3U)
#define ACPU_PLL_CTRL_0_ACPU_FBDIV_Msk		(0xfffUL << ACPU_PLL_CTRL_0_ACPU_FBDIV_Pos)
#define ACPU_PLL_CTRL_0_ACPU_FBDIV    		ACPU_PLL_CTRL_0_ACPU_FBDIV_Msk


#define ACPU_PLL_CTRL_0_ACPU_REFDIV_Pos		(15U)
#define ACPU_PLL_CTRL_0_ACPU_REFDIV_Msk		(0x3fUL << ACPU_PLL_CTRL_0_ACPU_REFDIV_Pos)
#define ACPU_PLL_CTRL_0_ACPU_REFDIV    		ACPU_PLL_CTRL_0_ACPU_REFDIV_Msk


#define ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Pos		(21U)
#define ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Msk		(0x7UL << ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Pos)
#define ACPU_PLL_CTRL_0_ACPU_POSTDIV2    		ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Msk


#define ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Pos		(24U)
#define ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Msk		(0x7UL << ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Pos)
#define ACPU_PLL_CTRL_0_ACPU_POSTDIV1    		ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Msk


#define ACPU_PLL_CTRL_0_ACPU_DSMEN_Pos		(27U)
#define ACPU_PLL_CTRL_0_ACPU_DSMEN_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_DSMEN_Pos)
#define ACPU_PLL_CTRL_0_ACPU_DSMEN    		ACPU_PLL_CTRL_0_ACPU_DSMEN_Msk


#define ACPU_PLL_CTRL_0_ACPU_DACEN_Pos		(28U)
#define ACPU_PLL_CTRL_0_ACPU_DACEN_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_DACEN_Pos)
#define ACPU_PLL_CTRL_0_ACPU_DACEN    		ACPU_PLL_CTRL_0_ACPU_DACEN_Msk


#define ACPU_PLL_CTRL_0_ACPU_BYPASS_Pos		(29U)
#define ACPU_PLL_CTRL_0_ACPU_BYPASS_Msk		(0x1UL << ACPU_PLL_CTRL_0_ACPU_BYPASS_Pos)
#define ACPU_PLL_CTRL_0_ACPU_BYPASS    		ACPU_PLL_CTRL_0_ACPU_BYPASS_Msk


/****************************** Bit definition for ACPU_PLL_CTRL_1 register ********************************/

#define ACPU_PLL_CTRL_1_ACPU_FRAC_Pos		(0U)
#define ACPU_PLL_CTRL_1_ACPU_FRAC_Msk		(0xffffffUL << ACPU_PLL_CTRL_1_ACPU_FRAC_Pos)
#define ACPU_PLL_CTRL_1_ACPU_FRAC    		ACPU_PLL_CTRL_1_ACPU_FRAC_Msk


/****************************** Bit definition for ACPU_PLL_CTRL_2 register ********************************/

#define ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Pos		(0U)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Msk		(0x1UL << ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Pos)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL    		ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Msk


#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Pos		(1U)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Msk		(0xfffUL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Pos)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN    		ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Msk


#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Pos		(13U)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Msk		(0x1UL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Pos)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN    		ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Msk


#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Pos		(14U)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Msk		(0x7UL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Pos)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT    		ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Msk


#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Pos		(17U)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Msk		(0x1UL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Pos)
#define ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP    		ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Msk


/****************************** Bit definition for ACPU_PLL_CTRL_3 register ********************************/

#define ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Pos		(0U)
#define ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Msk		(0xfffUL << ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Pos)
#define ACPU_PLL_CTRL_3_ACPU_TEST_CALIN    		ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Msk


#define ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Pos		(12U)
#define ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Msk		(0x1UL << ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Pos)
#define ACPU_PLL_CTRL_3_ACPU_SCANRSTB    		ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Msk


#define ACPU_PLL_CTRL_3_ACPU_SCANMODE_Pos		(13U)
#define ACPU_PLL_CTRL_3_ACPU_SCANMODE_Msk		(0x1UL << ACPU_PLL_CTRL_3_ACPU_SCANMODE_Pos)
#define ACPU_PLL_CTRL_3_ACPU_SCANMODE    		ACPU_PLL_CTRL_3_ACPU_SCANMODE_Msk


#define ACPU_PLL_CTRL_3_ACPU_SCANIN_Pos		(14U)
#define ACPU_PLL_CTRL_3_ACPU_SCANIN_Msk		(0x1UL << ACPU_PLL_CTRL_3_ACPU_SCANIN_Pos)
#define ACPU_PLL_CTRL_3_ACPU_SCANIN    		ACPU_PLL_CTRL_3_ACPU_SCANIN_Msk


#define ACPU_PLL_CTRL_3_ACPU_SCANEN_Pos		(15U)
#define ACPU_PLL_CTRL_3_ACPU_SCANEN_Msk		(0x1UL << ACPU_PLL_CTRL_3_ACPU_SCANEN_Pos)
#define ACPU_PLL_CTRL_3_ACPU_SCANEN    		ACPU_PLL_CTRL_3_ACPU_SCANEN_Msk


/****************************** Bit definition for ACPU_PLL_CTRL_4 register ********************************/

#define ACPU_PLL_CTRL_4_ACPU_PLLEN_Pos		(0U)
#define ACPU_PLL_CTRL_4_ACPU_PLLEN_Msk		(0x1UL << ACPU_PLL_CTRL_4_ACPU_PLLEN_Pos)
#define ACPU_PLL_CTRL_4_ACPU_PLLEN    		ACPU_PLL_CTRL_4_ACPU_PLLEN_Msk


#define ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Pos		(8U)
#define ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Msk		(0x1UL << ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Pos)
#define ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ    		ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Msk


/****************************** Bit definition for HS_PLL_CTRL_0 register ********************************/

#define HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Pos		(0U)
#define HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Msk		(0x1UL << HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Pos)
#define HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN    		HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Msk


#define HS_PLL_CTRL_0_HS_FOUTEN_Pos		(1U)
#define HS_PLL_CTRL_0_HS_FOUTEN_Msk		(0x1UL << HS_PLL_CTRL_0_HS_FOUTEN_Pos)
#define HS_PLL_CTRL_0_HS_FOUTEN    		HS_PLL_CTRL_0_HS_FOUTEN_Msk


#define HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Pos		(2U)
#define HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Msk		(0x1UL << HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Pos)
#define HS_PLL_CTRL_0_HS_FOUT4PHASEEN    		HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Msk


#define HS_PLL_CTRL_0_HS_FBDIV_Pos		(3U)
#define HS_PLL_CTRL_0_HS_FBDIV_Msk		(0xfffUL << HS_PLL_CTRL_0_HS_FBDIV_Pos)
#define HS_PLL_CTRL_0_HS_FBDIV    		HS_PLL_CTRL_0_HS_FBDIV_Msk


#define HS_PLL_CTRL_0_HS_REFDIV_Pos		(15U)
#define HS_PLL_CTRL_0_HS_REFDIV_Msk		(0x3fUL << HS_PLL_CTRL_0_HS_REFDIV_Pos)
#define HS_PLL_CTRL_0_HS_REFDIV    		HS_PLL_CTRL_0_HS_REFDIV_Msk


#define HS_PLL_CTRL_0_HS_POSTDIV2_Pos		(21U)
#define HS_PLL_CTRL_0_HS_POSTDIV2_Msk		(0x7UL << HS_PLL_CTRL_0_HS_POSTDIV2_Pos)
#define HS_PLL_CTRL_0_HS_POSTDIV2    		HS_PLL_CTRL_0_HS_POSTDIV2_Msk


#define HS_PLL_CTRL_0_HS_POSTDIV1_Pos		(24U)
#define HS_PLL_CTRL_0_HS_POSTDIV1_Msk		(0x7UL << HS_PLL_CTRL_0_HS_POSTDIV1_Pos)
#define HS_PLL_CTRL_0_HS_POSTDIV1    		HS_PLL_CTRL_0_HS_POSTDIV1_Msk


#define HS_PLL_CTRL_0_HS_DSMEN_Pos		(27U)
#define HS_PLL_CTRL_0_HS_DSMEN_Msk		(0x1UL << HS_PLL_CTRL_0_HS_DSMEN_Pos)
#define HS_PLL_CTRL_0_HS_DSMEN    		HS_PLL_CTRL_0_HS_DSMEN_Msk


#define HS_PLL_CTRL_0_HS_DACEN_Pos		(28U)
#define HS_PLL_CTRL_0_HS_DACEN_Msk		(0x1UL << HS_PLL_CTRL_0_HS_DACEN_Pos)
#define HS_PLL_CTRL_0_HS_DACEN    		HS_PLL_CTRL_0_HS_DACEN_Msk


#define HS_PLL_CTRL_0_HS_BYPASS_Pos		(29U)
#define HS_PLL_CTRL_0_HS_BYPASS_Msk		(0x1UL << HS_PLL_CTRL_0_HS_BYPASS_Pos)
#define HS_PLL_CTRL_0_HS_BYPASS    		HS_PLL_CTRL_0_HS_BYPASS_Msk


/****************************** Bit definition for HS_PLL_CTRL_1 register ********************************/

#define HS_PLL_CTRL_1_HS_FRAC_Pos		(0U)
#define HS_PLL_CTRL_1_HS_FRAC_Msk		(0xffffffUL << HS_PLL_CTRL_1_HS_FRAC_Pos)
#define HS_PLL_CTRL_1_HS_FRAC    		HS_PLL_CTRL_1_HS_FRAC_Msk


/****************************** Bit definition for HS_PLL_CTRL_2 register ********************************/

#define HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Pos		(0U)
#define HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Msk		(0x1UL << HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Pos)
#define HS_PLL_CTRL_2_HS_OFFSETFASTCAL    		HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Msk


#define HS_PLL_CTRL_2_HS_OFFSETCALIN_Pos		(1U)
#define HS_PLL_CTRL_2_HS_OFFSETCALIN_Msk		(0xfffUL << HS_PLL_CTRL_2_HS_OFFSETCALIN_Pos)
#define HS_PLL_CTRL_2_HS_OFFSETCALIN    		HS_PLL_CTRL_2_HS_OFFSETCALIN_Msk


#define HS_PLL_CTRL_2_HS_OFFSETCALEN_Pos		(13U)
#define HS_PLL_CTRL_2_HS_OFFSETCALEN_Msk		(0x1UL << HS_PLL_CTRL_2_HS_OFFSETCALEN_Pos)
#define HS_PLL_CTRL_2_HS_OFFSETCALEN    		HS_PLL_CTRL_2_HS_OFFSETCALEN_Msk


#define HS_PLL_CTRL_2_HS_OFFSETCALCNT_Pos		(14U)
#define HS_PLL_CTRL_2_HS_OFFSETCALCNT_Msk		(0x7UL << HS_PLL_CTRL_2_HS_OFFSETCALCNT_Pos)
#define HS_PLL_CTRL_2_HS_OFFSETCALCNT    		HS_PLL_CTRL_2_HS_OFFSETCALCNT_Msk


#define HS_PLL_CTRL_2_HS_OFFSETCALBYP_Pos		(17U)
#define HS_PLL_CTRL_2_HS_OFFSETCALBYP_Msk		(0x1UL << HS_PLL_CTRL_2_HS_OFFSETCALBYP_Pos)
#define HS_PLL_CTRL_2_HS_OFFSETCALBYP    		HS_PLL_CTRL_2_HS_OFFSETCALBYP_Msk


/****************************** Bit definition for HS_PLL_CTRL_3 register ********************************/

#define HS_PLL_CTRL_3_HS_TEST_CALIN_Pos		(0U)
#define HS_PLL_CTRL_3_HS_TEST_CALIN_Msk		(0xfffUL << HS_PLL_CTRL_3_HS_TEST_CALIN_Pos)
#define HS_PLL_CTRL_3_HS_TEST_CALIN    		HS_PLL_CTRL_3_HS_TEST_CALIN_Msk


#define HS_PLL_CTRL_3_HS_SCANRSTB_Pos		(12U)
#define HS_PLL_CTRL_3_HS_SCANRSTB_Msk		(0x1UL << HS_PLL_CTRL_3_HS_SCANRSTB_Pos)
#define HS_PLL_CTRL_3_HS_SCANRSTB    		HS_PLL_CTRL_3_HS_SCANRSTB_Msk


#define HS_PLL_CTRL_3_HS_SCANMODE_Pos		(13U)
#define HS_PLL_CTRL_3_HS_SCANMODE_Msk		(0x1UL << HS_PLL_CTRL_3_HS_SCANMODE_Pos)
#define HS_PLL_CTRL_3_HS_SCANMODE    		HS_PLL_CTRL_3_HS_SCANMODE_Msk


#define HS_PLL_CTRL_3_HS_SCANIN_Pos		(14U)
#define HS_PLL_CTRL_3_HS_SCANIN_Msk		(0x1UL << HS_PLL_CTRL_3_HS_SCANIN_Pos)
#define HS_PLL_CTRL_3_HS_SCANIN    		HS_PLL_CTRL_3_HS_SCANIN_Msk


#define HS_PLL_CTRL_3_HS_SCANEN_Pos		(15U)
#define HS_PLL_CTRL_3_HS_SCANEN_Msk		(0x1UL << HS_PLL_CTRL_3_HS_SCANEN_Pos)
#define HS_PLL_CTRL_3_HS_SCANEN    		HS_PLL_CTRL_3_HS_SCANEN_Msk


/****************************** Bit definition for HS_PLL_CTRL_4 register ********************************/

#define HS_PLL_CTRL_4_HS_PLLEN_Pos		(0U)
#define HS_PLL_CTRL_4_HS_PLLEN_Msk		(0x1UL << HS_PLL_CTRL_4_HS_PLLEN_Pos)
#define HS_PLL_CTRL_4_HS_PLLEN    		HS_PLL_CTRL_4_HS_PLLEN_Msk


#define HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Pos		(8U)
#define HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Msk		(0x1UL << HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Pos)
#define HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ    		HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Msk


/****************************** Bit definition for MEMORY_PLL_CTRL_0 register ********************************/

#define MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Pos		(0U)
#define MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Pos)
#define MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN    		MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Msk


#define MEMORY_PLL_CTRL_0_MEM_FOUTEN_Pos		(1U)
#define MEMORY_PLL_CTRL_0_MEM_FOUTEN_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_FOUTEN_Pos)
#define MEMORY_PLL_CTRL_0_MEM_FOUTEN    		MEMORY_PLL_CTRL_0_MEM_FOUTEN_Msk


#define MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Pos		(2U)
#define MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Pos)
#define MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN    		MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Msk


#define MEMORY_PLL_CTRL_0_MEM_FBDIV_Pos		(3U)
#define MEMORY_PLL_CTRL_0_MEM_FBDIV_Msk		(0xfffUL << MEMORY_PLL_CTRL_0_MEM_FBDIV_Pos)
#define MEMORY_PLL_CTRL_0_MEM_FBDIV    		MEMORY_PLL_CTRL_0_MEM_FBDIV_Msk


#define MEMORY_PLL_CTRL_0_MEM_REFDIV_Pos		(15U)
#define MEMORY_PLL_CTRL_0_MEM_REFDIV_Msk		(0x3fUL << MEMORY_PLL_CTRL_0_MEM_REFDIV_Pos)
#define MEMORY_PLL_CTRL_0_MEM_REFDIV    		MEMORY_PLL_CTRL_0_MEM_REFDIV_Msk


#define MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Pos		(21U)
#define MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Msk		(0x7UL << MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Pos)
#define MEMORY_PLL_CTRL_0_MEM_POSTDIV2    		MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Msk


#define MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Pos		(24U)
#define MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Msk		(0x7UL << MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Pos)
#define MEMORY_PLL_CTRL_0_MEM_POSTDIV1    		MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Msk


#define MEMORY_PLL_CTRL_0_MEM_DSMEN_Pos		(27U)
#define MEMORY_PLL_CTRL_0_MEM_DSMEN_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_DSMEN_Pos)
#define MEMORY_PLL_CTRL_0_MEM_DSMEN    		MEMORY_PLL_CTRL_0_MEM_DSMEN_Msk


#define MEMORY_PLL_CTRL_0_MEM_DACEN_Pos		(28U)
#define MEMORY_PLL_CTRL_0_MEM_DACEN_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_DACEN_Pos)
#define MEMORY_PLL_CTRL_0_MEM_DACEN    		MEMORY_PLL_CTRL_0_MEM_DACEN_Msk


#define MEMORY_PLL_CTRL_0_MEM_BYPASS_Pos		(29U)
#define MEMORY_PLL_CTRL_0_MEM_BYPASS_Msk		(0x1UL << MEMORY_PLL_CTRL_0_MEM_BYPASS_Pos)
#define MEMORY_PLL_CTRL_0_MEM_BYPASS    		MEMORY_PLL_CTRL_0_MEM_BYPASS_Msk


/****************************** Bit definition for MEMORY_PLL_CTRL_1 register ********************************/

#define MEMORY_PLL_CTRL_1_MEM_FRAC_Pos		(0U)
#define MEMORY_PLL_CTRL_1_MEM_FRAC_Msk		(0xffffffUL << MEMORY_PLL_CTRL_1_MEM_FRAC_Pos)
#define MEMORY_PLL_CTRL_1_MEM_FRAC    		MEMORY_PLL_CTRL_1_MEM_FRAC_Msk


/****************************** Bit definition for MEMORY_PLL_CTRL_2 register ********************************/

#define MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Pos		(0U)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Msk		(0x1UL << MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Pos)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL    		MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Msk


#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Pos		(1U)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Msk		(0xfffUL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Pos)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN    		MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Msk


#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Pos		(13U)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Msk		(0x1UL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Pos)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN    		MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Msk


#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Pos		(14U)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Msk		(0x7UL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Pos)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT    		MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Msk


#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Pos		(17U)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Msk		(0x1UL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Pos)
#define MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP    		MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Msk


/****************************** Bit definition for MEMORY_PLL_CTRL_3 register ********************************/

#define MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Pos		(0U)
#define MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Msk		(0xfffUL << MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Pos)
#define MEMORY_PLL_CTRL_3_MEM_TEST_CALIN    		MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Msk


#define MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Pos		(12U)
#define MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Msk		(0x1UL << MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Pos)
#define MEMORY_PLL_CTRL_3_MEM_SCANRSTB    		MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Msk


#define MEMORY_PLL_CTRL_3_MEM_SCANMODE_Pos		(13U)
#define MEMORY_PLL_CTRL_3_MEM_SCANMODE_Msk		(0x1UL << MEMORY_PLL_CTRL_3_MEM_SCANMODE_Pos)
#define MEMORY_PLL_CTRL_3_MEM_SCANMODE    		MEMORY_PLL_CTRL_3_MEM_SCANMODE_Msk


#define MEMORY_PLL_CTRL_3_MEM_SCANIN_Pos		(14U)
#define MEMORY_PLL_CTRL_3_MEM_SCANIN_Msk		(0x1UL << MEMORY_PLL_CTRL_3_MEM_SCANIN_Pos)
#define MEMORY_PLL_CTRL_3_MEM_SCANIN    		MEMORY_PLL_CTRL_3_MEM_SCANIN_Msk


#define MEMORY_PLL_CTRL_3_MEM_SCANEN_Pos		(15U)
#define MEMORY_PLL_CTRL_3_MEM_SCANEN_Msk		(0x1UL << MEMORY_PLL_CTRL_3_MEM_SCANEN_Pos)
#define MEMORY_PLL_CTRL_3_MEM_SCANEN    		MEMORY_PLL_CTRL_3_MEM_SCANEN_Msk


/****************************** Bit definition for MEMORY_PLL_CTRL_4 register ********************************/

#define MEMORY_PLL_CTRL_4_MEM_PLLEN_Pos		(0U)
#define MEMORY_PLL_CTRL_4_MEM_PLLEN_Msk		(0x1UL << MEMORY_PLL_CTRL_4_MEM_PLLEN_Pos)
#define MEMORY_PLL_CTRL_4_MEM_PLLEN    		MEMORY_PLL_CTRL_4_MEM_PLLEN_Msk


#define MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Pos		(8U)
#define MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Msk		(0x1UL << MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Pos)
#define MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ    		MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Msk


/****************************** Bit definition for MCPU_PLL_CTRL_0 register ********************************/

#define MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Pos		(0U)
#define MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Pos)
#define MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN    		MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Msk


#define MCPU_PLL_CTRL_0_MCPU_FOUTEN_Pos		(1U)
#define MCPU_PLL_CTRL_0_MCPU_FOUTEN_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_FOUTEN_Pos)
#define MCPU_PLL_CTRL_0_MCPU_FOUTEN    		MCPU_PLL_CTRL_0_MCPU_FOUTEN_Msk


#define MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Pos		(2U)
#define MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Pos)
#define MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN    		MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Msk


#define MCPU_PLL_CTRL_0_MCPU_FBDIV_Pos		(3U)
#define MCPU_PLL_CTRL_0_MCPU_FBDIV_Msk		(0xfffUL << MCPU_PLL_CTRL_0_MCPU_FBDIV_Pos)
#define MCPU_PLL_CTRL_0_MCPU_FBDIV    		MCPU_PLL_CTRL_0_MCPU_FBDIV_Msk


#define MCPU_PLL_CTRL_0_MCPU_REFDIV_Pos		(15U)
#define MCPU_PLL_CTRL_0_MCPU_REFDIV_Msk		(0x3fUL << MCPU_PLL_CTRL_0_MCPU_REFDIV_Pos)
#define MCPU_PLL_CTRL_0_MCPU_REFDIV    		MCPU_PLL_CTRL_0_MCPU_REFDIV_Msk


#define MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Pos		(21U)
#define MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Msk		(0x7UL << MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Pos)
#define MCPU_PLL_CTRL_0_MCPU_POSTDIV2    		MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Msk


#define MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Pos		(24U)
#define MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Msk		(0x7UL << MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Pos)
#define MCPU_PLL_CTRL_0_MCPU_POSTDIV1    		MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Msk


#define MCPU_PLL_CTRL_0_MCPU_DSMEN_Pos		(27U)
#define MCPU_PLL_CTRL_0_MCPU_DSMEN_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_DSMEN_Pos)
#define MCPU_PLL_CTRL_0_MCPU_DSMEN    		MCPU_PLL_CTRL_0_MCPU_DSMEN_Msk


#define MCPU_PLL_CTRL_0_MCPU_DACEN_Pos		(28U)
#define MCPU_PLL_CTRL_0_MCPU_DACEN_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_DACEN_Pos)
#define MCPU_PLL_CTRL_0_MCPU_DACEN    		MCPU_PLL_CTRL_0_MCPU_DACEN_Msk


#define MCPU_PLL_CTRL_0_MCPU_BYPASS_Pos		(29U)
#define MCPU_PLL_CTRL_0_MCPU_BYPASS_Msk		(0x1UL << MCPU_PLL_CTRL_0_MCPU_BYPASS_Pos)
#define MCPU_PLL_CTRL_0_MCPU_BYPASS    		MCPU_PLL_CTRL_0_MCPU_BYPASS_Msk


/****************************** Bit definition for MCPU_PLL_CTRL_1 register ********************************/

#define MCPU_PLL_CTRL_1_MCPU_FRAC_Pos		(0U)
#define MCPU_PLL_CTRL_1_MCPU_FRAC_Msk		(0xffffffUL << MCPU_PLL_CTRL_1_MCPU_FRAC_Pos)
#define MCPU_PLL_CTRL_1_MCPU_FRAC    		MCPU_PLL_CTRL_1_MCPU_FRAC_Msk


/****************************** Bit definition for MCPU_PLL_CTRL_2 register ********************************/

#define MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Pos		(0U)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Msk		(0x1UL << MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Pos)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL    		MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Msk


#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Pos		(1U)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Msk		(0xfffUL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Pos)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN    		MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Msk


#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Pos		(13U)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Msk		(0x1UL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Pos)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN    		MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Msk


#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Pos		(14U)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Msk		(0x7UL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Pos)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT    		MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Msk


#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Pos		(17U)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Msk		(0x1UL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Pos)
#define MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP    		MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Msk


/****************************** Bit definition for MCPU_PLL_CTRL_3 register ********************************/

#define MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Pos		(0U)
#define MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Msk		(0xfffUL << MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Pos)
#define MCPU_PLL_CTRL_3_MCPU_TEST_CALIN    		MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Msk


#define MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Pos		(12U)
#define MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Msk		(0x1UL << MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Pos)
#define MCPU_PLL_CTRL_3_MCPU_SCANRSTB    		MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Msk


#define MCPU_PLL_CTRL_3_MCPU_SCANMODE_Pos		(13U)
#define MCPU_PLL_CTRL_3_MCPU_SCANMODE_Msk		(0x1UL << MCPU_PLL_CTRL_3_MCPU_SCANMODE_Pos)
#define MCPU_PLL_CTRL_3_MCPU_SCANMODE    		MCPU_PLL_CTRL_3_MCPU_SCANMODE_Msk


#define MCPU_PLL_CTRL_3_MCPU_SCANIN_Pos		(14U)
#define MCPU_PLL_CTRL_3_MCPU_SCANIN_Msk		(0x1UL << MCPU_PLL_CTRL_3_MCPU_SCANIN_Pos)
#define MCPU_PLL_CTRL_3_MCPU_SCANIN    		MCPU_PLL_CTRL_3_MCPU_SCANIN_Msk


#define MCPU_PLL_CTRL_3_MCPU_SCANEN_Pos		(15U)
#define MCPU_PLL_CTRL_3_MCPU_SCANEN_Msk		(0x1UL << MCPU_PLL_CTRL_3_MCPU_SCANEN_Pos)
#define MCPU_PLL_CTRL_3_MCPU_SCANEN    		MCPU_PLL_CTRL_3_MCPU_SCANEN_Msk


/****************************** Bit definition for MCPU_PLL_CTRL_4 register ********************************/

#define MCPU_PLL_CTRL_4_MCPU_PLLEN_Pos		(0U)
#define MCPU_PLL_CTRL_4_MCPU_PLLEN_Msk		(0x1UL << MCPU_PLL_CTRL_4_MCPU_PLLEN_Pos)
#define MCPU_PLL_CTRL_4_MCPU_PLLEN    		MCPU_PLL_CTRL_4_MCPU_PLLEN_Msk


#define MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Pos		(8U)
#define MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Msk		(0x1UL << MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Pos)
#define MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ    		MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Msk


/****************************** Bit definition for PERIPH_DIV register ********************************/

#define PERIPH_DIV_DIV_Pos		(0U)
#define PERIPH_DIV_DIV_Msk		(0xfUL << PERIPH_DIV_DIV_Pos)
#define PERIPH_DIV_DIV    		PERIPH_DIV_DIV_Msk


/****************************** Bit definition for GATING_CONTROL register ********************************/

#define GATING_CONTROL_CG_MEM_Pos		(0U)
#define GATING_CONTROL_CG_MEM_Msk		(0x1UL << GATING_CONTROL_CG_MEM_Pos)
#define GATING_CONTROL_CG_MEM    		GATING_CONTROL_CG_MEM_Msk


#define GATING_CONTROL_CG_HS_Pos		(1U)
#define GATING_CONTROL_CG_HS_Msk		(0x1UL << GATING_CONTROL_CG_HS_Pos)
#define GATING_CONTROL_CG_HS    		GATING_CONTROL_CG_HS_Msk


#define GATING_CONTROL_CG_ACPU_Pos		(2U)
#define GATING_CONTROL_CG_ACPU_Msk		(0x1UL << GATING_CONTROL_CG_ACPU_Pos)
#define GATING_CONTROL_CG_ACPU    		GATING_CONTROL_CG_ACPU_Msk


/****************************** Bit definition for BOOTSTRAP_STATUS register ********************************/

#define BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Pos		(0U)
#define BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Msk		(0x1UL << BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Pos)
#define BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS    		BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Msk


#define BOOTSTRAP_STATUS_BOOTM_Pos		(1U)
#define BOOTSTRAP_STATUS_BOOTM_Msk		(0x3UL << BOOTSTRAP_STATUS_BOOTM_Pos)
#define BOOTSTRAP_STATUS_BOOTM    		BOOTSTRAP_STATUS_BOOTM_Msk


#define BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Pos		(3U)
#define BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Msk		(0x1UL << BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Pos)
#define BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS    		BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Msk


#define BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Pos		(4U)
#define BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Msk		(0x1UL << BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Pos)
#define BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS    		BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Msk


#define BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Pos		(5U)
#define BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Msk		(0x1UL << BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Pos)
#define BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS    		BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Msk


#define BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Pos		(6U)
#define BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Msk		(0x1UL << BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Pos)
#define BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS    		BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Msk


#define BOOTSTRAP_STATUS_SW_CONTROL_Pos		(8U)
#define BOOTSTRAP_STATUS_SW_CONTROL_Msk		(0x1UL << BOOTSTRAP_STATUS_SW_CONTROL_Pos)
#define BOOTSTRAP_STATUS_SW_CONTROL    		BOOTSTRAP_STATUS_SW_CONTROL_Msk


/****************************** Bit definition for ACPU_PLL_STATUS register ********************************/

#define ACPU_PLL_STATUS_ACPU_LOCK_Pos		(0U)
#define ACPU_PLL_STATUS_ACPU_LOCK_Msk		(0x1UL << ACPU_PLL_STATUS_ACPU_LOCK_Pos)
#define ACPU_PLL_STATUS_ACPU_LOCK    		ACPU_PLL_STATUS_ACPU_LOCK_Msk


#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Pos		(1U)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Msk		(0x1UL << ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Pos)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK    		ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Msk


#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Pos		(2U)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Msk		(0x7UL << ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Pos)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT    		ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Msk


#define ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Pos		(5U)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Msk		(0xfffUL << ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Pos)
#define ACPU_PLL_STATUS_ACPU_OFFSETCALOUT    		ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Msk


#define ACPU_PLL_STATUS_ACPU_SCANOUT_Pos		(17U)
#define ACPU_PLL_STATUS_ACPU_SCANOUT_Msk		(0x1UL << ACPU_PLL_STATUS_ACPU_SCANOUT_Pos)
#define ACPU_PLL_STATUS_ACPU_SCANOUT    		ACPU_PLL_STATUS_ACPU_SCANOUT_Msk


#define ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Pos		(18U)
#define ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Msk		(0xfffUL << ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Pos)
#define ACPU_PLL_STATUS_ACPU_TEST_CALOUT    		ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Msk


/****************************** Bit definition for HS_PLL_STATUS register ********************************/

#define HS_PLL_STATUS_LOCK_Pos		(0U)
#define HS_PLL_STATUS_LOCK_Msk		(0x1UL << HS_PLL_STATUS_LOCK_Pos)
#define HS_PLL_STATUS_LOCK    		HS_PLL_STATUS_LOCK_Msk


#define HS_PLL_STATUS_HS_OFFSETCALLOCK_Pos		(1U)
#define HS_PLL_STATUS_HS_OFFSETCALLOCK_Msk		(0x1UL << HS_PLL_STATUS_HS_OFFSETCALLOCK_Pos)
#define HS_PLL_STATUS_HS_OFFSETCALLOCK    		HS_PLL_STATUS_HS_OFFSETCALLOCK_Msk


#define HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Pos		(2U)
#define HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Msk		(0x7UL << HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Pos)
#define HS_PLL_STATUS_HS_OFFSETCALLOCKCNT    		HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Msk


#define HS_PLL_STATUS_HS_OFFSETCALOUT_Pos		(5U)
#define HS_PLL_STATUS_HS_OFFSETCALOUT_Msk		(0xfffUL << HS_PLL_STATUS_HS_OFFSETCALOUT_Pos)
#define HS_PLL_STATUS_HS_OFFSETCALOUT    		HS_PLL_STATUS_HS_OFFSETCALOUT_Msk


#define HS_PLL_STATUS_HS_SCANOUT_Pos		(17U)
#define HS_PLL_STATUS_HS_SCANOUT_Msk		(0x1UL << HS_PLL_STATUS_HS_SCANOUT_Pos)
#define HS_PLL_STATUS_HS_SCANOUT    		HS_PLL_STATUS_HS_SCANOUT_Msk


#define HS_PLL_STATUS_HS_TEST_CALOUT_Pos		(18U)
#define HS_PLL_STATUS_HS_TEST_CALOUT_Msk		(0xfffUL << HS_PLL_STATUS_HS_TEST_CALOUT_Pos)
#define HS_PLL_STATUS_HS_TEST_CALOUT    		HS_PLL_STATUS_HS_TEST_CALOUT_Msk


/****************************** Bit definition for MEM_PLL_STATUS register ********************************/

#define MEM_PLL_STATUS_MEM_LOCK_Pos		(0U)
#define MEM_PLL_STATUS_MEM_LOCK_Msk		(0x1UL << MEM_PLL_STATUS_MEM_LOCK_Pos)
#define MEM_PLL_STATUS_MEM_LOCK    		MEM_PLL_STATUS_MEM_LOCK_Msk


#define MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Pos		(1U)
#define MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Msk		(0x1UL << MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Pos)
#define MEM_PLL_STATUS_MEM_OFFSETCALLOCK    		MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Msk


#define MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Pos		(2U)
#define MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Msk		(0x7UL << MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Pos)
#define MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT    		MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Msk


#define MEM_PLL_STATUS_MEM_OFFSETCALOUT_Pos		(5U)
#define MEM_PLL_STATUS_MEM_OFFSETCALOUT_Msk		(0xfffUL << MEM_PLL_STATUS_MEM_OFFSETCALOUT_Pos)
#define MEM_PLL_STATUS_MEM_OFFSETCALOUT    		MEM_PLL_STATUS_MEM_OFFSETCALOUT_Msk


#define MEM_PLL_STATUS_MEM_SCANOUT_Pos		(17U)
#define MEM_PLL_STATUS_MEM_SCANOUT_Msk		(0x1UL << MEM_PLL_STATUS_MEM_SCANOUT_Pos)
#define MEM_PLL_STATUS_MEM_SCANOUT    		MEM_PLL_STATUS_MEM_SCANOUT_Msk


#define MEM_PLL_STATUS_MEM_TEST_CALOUT_Pos		(18U)
#define MEM_PLL_STATUS_MEM_TEST_CALOUT_Msk		(0xfffUL << MEM_PLL_STATUS_MEM_TEST_CALOUT_Pos)
#define MEM_PLL_STATUS_MEM_TEST_CALOUT    		MEM_PLL_STATUS_MEM_TEST_CALOUT_Msk


/****************************** Bit definition for MCPU_PLL_STATUS register ********************************/

#define MCPU_PLL_STATUS_MCPU_LOCK_Pos		(0U)
#define MCPU_PLL_STATUS_MCPU_LOCK_Msk		(0x1UL << MCPU_PLL_STATUS_MCPU_LOCK_Pos)
#define MCPU_PLL_STATUS_MCPU_LOCK    		MCPU_PLL_STATUS_MCPU_LOCK_Msk


#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Pos		(1U)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Msk		(0x1UL << MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Pos)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK    		MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Msk


#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Pos		(2U)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Msk		(0x7UL << MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Pos)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT    		MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Msk


#define MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Pos		(5U)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Msk		(0xfffUL << MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Pos)
#define MCPU_PLL_STATUS_MCPU_OFFSETCALOUT    		MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Msk


#define MCPU_PLL_STATUS_MCPU_SCANOUT_Pos		(17U)
#define MCPU_PLL_STATUS_MCPU_SCANOUT_Msk		(0x1UL << MCPU_PLL_STATUS_MCPU_SCANOUT_Pos)
#define MCPU_PLL_STATUS_MCPU_SCANOUT    		MCPU_PLL_STATUS_MCPU_SCANOUT_Msk


#define MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Pos		(18U)
#define MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Msk		(0xfffUL << MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Pos)
#define MCPU_PLL_STATUS_MCPU_TEST_CALOUT    		MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_0 register ********************************/

#define IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Pos)
#define IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0    		IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Msk


#define IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Pos)
#define IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0    		IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_1 register ********************************/

#define IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Pos)
#define IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1    		IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Msk


#define IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Pos)
#define IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1    		IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_2 register ********************************/

#define IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Pos)
#define IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2    		IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Msk


#define IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Pos)
#define IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2    		IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_3 register ********************************/

#define IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Pos)
#define IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3    		IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Msk


#define IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Pos)
#define IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3    		IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_4 register ********************************/

#define IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Pos)
#define IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4    		IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Msk


#define IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Pos)
#define IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4    		IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_5 register ********************************/

#define IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Pos)
#define IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5    		IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Msk


#define IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Pos)
#define IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5    		IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_6 register ********************************/

#define IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Pos)
#define IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6    		IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Msk


#define IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Pos)
#define IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6    		IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_7 register ********************************/

#define IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Pos)
#define IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7    		IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Msk


#define IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Pos)
#define IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7    		IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_8 register ********************************/

#define IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Pos)
#define IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8    		IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Msk


#define IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Pos)
#define IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8    		IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_9 register ********************************/

#define IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Pos)
#define IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9    		IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Msk


#define IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Pos)
#define IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9    		IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_10 register ********************************/

#define IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Pos)
#define IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10    		IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Msk


#define IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Pos)
#define IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10    		IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_11 register ********************************/

#define IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Pos)
#define IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11    		IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Msk


#define IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Pos)
#define IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11    		IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_12 register ********************************/

#define IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Pos)
#define IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12    		IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Msk


#define IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Pos)
#define IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12    		IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_13 register ********************************/

#define IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Pos)
#define IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13    		IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Msk


#define IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Pos)
#define IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13    		IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_14 register ********************************/

#define IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Pos)
#define IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14    		IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Msk


#define IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Pos)
#define IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14    		IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_15 register ********************************/

#define IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Pos)
#define IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15    		IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Msk


#define IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Pos)
#define IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15    		IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_16 register ********************************/

#define IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Pos)
#define IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16    		IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Msk


#define IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Pos)
#define IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16    		IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_17 register ********************************/

#define IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Pos)
#define IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17    		IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Msk


#define IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Pos)
#define IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17    		IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_18 register ********************************/

#define IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Pos)
#define IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18    		IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Msk


#define IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Pos)
#define IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18    		IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_19 register ********************************/

#define IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Pos)
#define IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19    		IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Msk


#define IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Pos)
#define IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19    		IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_20 register ********************************/

#define IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Pos)
#define IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20    		IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Msk


#define IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Pos)
#define IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20    		IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_21 register ********************************/

#define IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Pos)
#define IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21    		IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Msk


#define IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Pos)
#define IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21    		IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_22 register ********************************/

#define IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Pos)
#define IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22    		IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Msk


#define IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Pos)
#define IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22    		IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_23 register ********************************/

#define IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Pos)
#define IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23    		IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Msk


#define IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Pos)
#define IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23    		IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_24 register ********************************/

#define IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Pos)
#define IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24    		IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Msk


#define IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Pos)
#define IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24    		IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_25 register ********************************/

#define IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Pos)
#define IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25    		IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Msk


#define IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Pos)
#define IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25    		IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_26 register ********************************/

#define IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Pos)
#define IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26    		IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Msk


#define IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Pos)
#define IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26    		IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_27 register ********************************/

#define IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Pos)
#define IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27    		IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Msk


#define IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Pos)
#define IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27    		IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_28 register ********************************/

#define IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Pos)
#define IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28    		IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Msk


#define IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Pos)
#define IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28    		IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_29 register ********************************/

#define IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Pos)
#define IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29    		IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Msk


#define IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Pos)
#define IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29    		IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_30 register ********************************/

#define IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Pos)
#define IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30    		IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Msk


#define IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Pos)
#define IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30    		IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_31 register ********************************/

#define IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Pos)
#define IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31    		IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Msk


#define IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Pos)
#define IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31    		IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_32 register ********************************/

#define IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Pos)
#define IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32    		IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Msk


#define IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Pos)
#define IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32    		IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_33 register ********************************/

#define IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Pos)
#define IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33    		IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Msk


#define IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Pos)
#define IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33    		IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_34 register ********************************/

#define IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Pos)
#define IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34    		IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Msk


#define IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Pos)
#define IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34    		IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_35 register ********************************/

#define IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Pos)
#define IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35    		IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Msk


#define IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Pos)
#define IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35    		IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_36 register ********************************/

#define IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Pos)
#define IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36    		IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Msk


#define IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Pos)
#define IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36    		IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_37 register ********************************/

#define IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Pos)
#define IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37    		IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Msk


#define IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Pos)
#define IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37    		IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_38 register ********************************/

#define IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Pos)
#define IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38    		IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Msk


#define IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Pos)
#define IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38    		IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_39 register ********************************/

#define IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Pos)
#define IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39    		IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Msk


#define IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Pos)
#define IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39    		IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_40 register ********************************/

#define IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Pos)
#define IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40    		IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Msk


#define IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Pos)
#define IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40    		IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_41 register ********************************/

#define IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Pos)
#define IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41    		IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Msk


#define IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Pos)
#define IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41    		IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_42 register ********************************/

#define IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Pos)
#define IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42    		IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Msk


#define IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Pos)
#define IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42    		IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_43 register ********************************/

#define IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Pos)
#define IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43    		IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Msk


#define IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Pos)
#define IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43    		IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_44 register ********************************/

#define IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Pos)
#define IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44    		IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Msk


#define IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Pos)
#define IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44    		IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_45 register ********************************/

#define IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Pos)
#define IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45    		IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Msk


#define IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Pos)
#define IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45    		IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_46 register ********************************/

#define IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Pos)
#define IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46    		IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Msk


#define IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Pos)
#define IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46    		IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_47 register ********************************/

#define IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Pos)
#define IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47    		IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Msk


#define IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Pos)
#define IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47    		IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_48 register ********************************/

#define IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Pos)
#define IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48    		IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Msk


#define IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Pos)
#define IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48    		IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_49 register ********************************/

#define IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Pos)
#define IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49    		IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Msk


#define IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Pos)
#define IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49    		IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_50 register ********************************/

#define IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Pos)
#define IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50    		IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Msk


#define IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Pos)
#define IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50    		IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_51 register ********************************/

#define IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Pos)
#define IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51    		IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Msk


#define IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Pos)
#define IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51    		IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_52 register ********************************/

#define IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Pos)
#define IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52    		IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Msk


#define IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Pos)
#define IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52    		IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_53 register ********************************/

#define IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Pos)
#define IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53    		IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Msk


#define IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Pos)
#define IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53    		IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_54 register ********************************/

#define IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Pos)
#define IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54    		IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Msk


#define IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Pos)
#define IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54    		IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_55 register ********************************/

#define IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Pos)
#define IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55    		IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Msk


#define IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Pos)
#define IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55    		IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_56 register ********************************/

#define IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Pos)
#define IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56    		IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Msk


#define IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Pos)
#define IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56    		IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_57 register ********************************/

#define IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Pos)
#define IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57    		IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Msk


#define IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Pos)
#define IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57    		IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_58 register ********************************/

#define IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Pos)
#define IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58    		IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Msk


#define IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Pos)
#define IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58    		IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_59 register ********************************/

#define IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Pos)
#define IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59    		IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Msk


#define IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Pos)
#define IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59    		IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_60 register ********************************/

#define IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Pos)
#define IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60    		IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Msk


#define IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Pos)
#define IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60    		IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_61 register ********************************/

#define IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Pos)
#define IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61    		IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Msk


#define IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Pos)
#define IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61    		IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_62 register ********************************/

#define IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Pos)
#define IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62    		IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Msk


#define IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Pos)
#define IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62    		IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Msk


/****************************** Bit definition for IRQ_MASK_MAP_CONTROL_63 register ********************************/

#define IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Pos		(0U)
#define IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Msk		(0x1UL << IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Pos)
#define IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63    		IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Msk


#define IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Pos		(16U)
#define IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Msk		(0x3UL << IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Pos)
#define IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63    		IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Msk


/****************************** Bit definition for AXI_CLK_EN_M0 register ********************************/

#define AXI_CLK_EN_M0_AXI_CLK_EN_M0_Pos		(0U)
#define AXI_CLK_EN_M0_AXI_CLK_EN_M0_Msk		(0x1UL << AXI_CLK_EN_M0_AXI_CLK_EN_M0_Pos)
#define AXI_CLK_EN_M0_AXI_CLK_EN_M0    		AXI_CLK_EN_M0_AXI_CLK_EN_M0_Msk


/****************************** Bit definition for AXI_CLK_EN_M1 register ********************************/

#define AXI_CLK_EN_M1_AXI_CLK_EN_M1_Pos		(0U)
#define AXI_CLK_EN_M1_AXI_CLK_EN_M1_Msk		(0x1UL << AXI_CLK_EN_M1_AXI_CLK_EN_M1_Pos)
#define AXI_CLK_EN_M1_AXI_CLK_EN_M1    		AXI_CLK_EN_M1_AXI_CLK_EN_M1_Msk


/****************************** Bit definition for AXI_CLK_EN_M2 register ********************************/

#define AXI_CLK_EN_M2_AXI_CLK_EN_M2_Pos		(0U)
#define AXI_CLK_EN_M2_AXI_CLK_EN_M2_Msk		(0x1UL << AXI_CLK_EN_M2_AXI_CLK_EN_M2_Pos)
#define AXI_CLK_EN_M2_AXI_CLK_EN_M2    		AXI_CLK_EN_M2_AXI_CLK_EN_M2_Msk


/****************************** Bit definition for AXI_CLK_EN_M3 register ********************************/

#define AXI_CLK_EN_M3_AXI_CLK_EN_M3_Pos		(0U)
#define AXI_CLK_EN_M3_AXI_CLK_EN_M3_Msk		(0x1UL << AXI_CLK_EN_M3_AXI_CLK_EN_M3_Pos)
#define AXI_CLK_EN_M3_AXI_CLK_EN_M3    		AXI_CLK_EN_M3_AXI_CLK_EN_M3_Msk


/****************************** Bit definition for ACPU_PM_STATUS register ********************************/

#define ACPU_PM_STATUS_STANDBY_WFI_L3_Pos		(0U)
#define ACPU_PM_STATUS_STANDBY_WFI_L3_Msk		(0xfUL << ACPU_PM_STATUS_STANDBY_WFI_L3_Pos)
#define ACPU_PM_STATUS_STANDBY_WFI_L3    		ACPU_PM_STATUS_STANDBY_WFI_L3_Msk


#define ACPU_PM_STATUS_STANDBY_WFI_Pos		(4U)
#define ACPU_PM_STATUS_STANDBY_WFI_Msk		(0xffffUL << ACPU_PM_STATUS_STANDBY_WFI_Pos)
#define ACPU_PM_STATUS_STANDBY_WFI    		ACPU_PM_STATUS_STANDBY_WFI_Msk


/****************************** Bit definition for BOOT_SSI_XIP_EN register ********************************/

#define BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Pos		(0U)
#define BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Msk		(0x1UL << BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Pos)
#define BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN    		BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Msk


/****************************** Bit definition for BOOT_SSI_STATUS register ********************************/

#define BOOT_SSI_STATUS_BOOT_SSI_BUSY_Pos		(0U)
#define BOOT_SSI_STATUS_BOOT_SSI_BUSY_Msk		(0x1UL << BOOT_SSI_STATUS_BOOT_SSI_BUSY_Pos)
#define BOOT_SSI_STATUS_BOOT_SSI_BUSY    		BOOT_SSI_STATUS_BOOT_SSI_BUSY_Msk


#define BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Pos		(1U)
#define BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Msk		(0x1UL << BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Pos)
#define BOOT_SSI_STATUS_BOOT_SSI_SLEEP    		BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Msk


/****************************** Bit definition for GP_SSI_STATUS register ********************************/

#define GP_SSI_STATUS_GP_SSI_BUSY_Pos		(0U)
#define GP_SSI_STATUS_GP_SSI_BUSY_Msk		(0x1UL << GP_SSI_STATUS_GP_SSI_BUSY_Pos)
#define GP_SSI_STATUS_GP_SSI_BUSY    		GP_SSI_STATUS_GP_SSI_BUSY_Msk


#define GP_SSI_STATUS_GP_SSI_SLEEP_Pos		(1U)
#define GP_SSI_STATUS_GP_SSI_SLEEP_Msk		(0x1UL << GP_SSI_STATUS_GP_SSI_SLEEP_Pos)
#define GP_SSI_STATUS_GP_SSI_SLEEP    		GP_SSI_STATUS_GP_SSI_SLEEP_Msk


/****************************** Bit definition for I2C_STATUS register ********************************/

#define I2C_STATUS_DEBUG_HS_Pos		(0U)
#define I2C_STATUS_DEBUG_HS_Msk		(0x1UL << I2C_STATUS_DEBUG_HS_Pos)
#define I2C_STATUS_DEBUG_HS    		I2C_STATUS_DEBUG_HS_Msk


#define I2C_STATUS_DEBUG_WR_Pos		(1U)
#define I2C_STATUS_DEBUG_WR_Msk		(0x1UL << I2C_STATUS_DEBUG_WR_Pos)
#define I2C_STATUS_DEBUG_WR    		I2C_STATUS_DEBUG_WR_Msk


#define I2C_STATUS_DEBUG_RD_Pos		(2U)
#define I2C_STATUS_DEBUG_RD_Msk		(0x1UL << I2C_STATUS_DEBUG_RD_Pos)
#define I2C_STATUS_DEBUG_RD    		I2C_STATUS_DEBUG_RD_Msk


#define I2C_STATUS_DEBUG_ADDR_Pos		(3U)
#define I2C_STATUS_DEBUG_ADDR_Msk		(0x1UL << I2C_STATUS_DEBUG_ADDR_Pos)
#define I2C_STATUS_DEBUG_ADDR    		I2C_STATUS_DEBUG_ADDR_Msk


#define I2C_STATUS_DEBUG_DATA_Pos		(4U)
#define I2C_STATUS_DEBUG_DATA_Msk		(0x1UL << I2C_STATUS_DEBUG_DATA_Pos)
#define I2C_STATUS_DEBUG_DATA    		I2C_STATUS_DEBUG_DATA_Msk


#define I2C_STATUS_DEBUG_P_GEN_Pos		(5U)
#define I2C_STATUS_DEBUG_P_GEN_Msk		(0x1UL << I2C_STATUS_DEBUG_P_GEN_Pos)
#define I2C_STATUS_DEBUG_P_GEN    		I2C_STATUS_DEBUG_P_GEN_Msk


#define I2C_STATUS_DEBUG_S_GEN_Pos		(6U)
#define I2C_STATUS_DEBUG_S_GEN_Msk		(0x1UL << I2C_STATUS_DEBUG_S_GEN_Pos)
#define I2C_STATUS_DEBUG_S_GEN    		I2C_STATUS_DEBUG_S_GEN_Msk


#define I2C_STATUS_DEGUB_SLV_CSTATE_Pos		(7U)
#define I2C_STATUS_DEGUB_SLV_CSTATE_Msk		(0xfUL << I2C_STATUS_DEGUB_SLV_CSTATE_Pos)
#define I2C_STATUS_DEGUB_SLV_CSTATE    		I2C_STATUS_DEGUB_SLV_CSTATE_Msk


#define I2C_STATUS_DEGUB_MST_CSTATE_Pos		(11U)
#define I2C_STATUS_DEGUB_MST_CSTATE_Msk		(0x1fUL << I2C_STATUS_DEGUB_MST_CSTATE_Pos)
#define I2C_STATUS_DEGUB_MST_CSTATE    		I2C_STATUS_DEGUB_MST_CSTATE_Msk


#define I2C_STATUS_DEBUG_ADDR_10BIT_Pos		(16U)
#define I2C_STATUS_DEBUG_ADDR_10BIT_Msk		(0x1UL << I2C_STATUS_DEBUG_ADDR_10BIT_Pos)
#define I2C_STATUS_DEBUG_ADDR_10BIT    		I2C_STATUS_DEBUG_ADDR_10BIT_Msk


#define I2C_STATUS_DEBUG_SLAVE_ACT_Pos		(17U)
#define I2C_STATUS_DEBUG_SLAVE_ACT_Msk		(0x1UL << I2C_STATUS_DEBUG_SLAVE_ACT_Pos)
#define I2C_STATUS_DEBUG_SLAVE_ACT    		I2C_STATUS_DEBUG_SLAVE_ACT_Msk


#define I2C_STATUS_DEBUG_MASTER_ACT_Pos		(18U)
#define I2C_STATUS_DEBUG_MASTER_ACT_Msk		(0x1UL << I2C_STATUS_DEBUG_MASTER_ACT_Pos)
#define I2C_STATUS_DEBUG_MASTER_ACT    		I2C_STATUS_DEBUG_MASTER_ACT_Msk


#define I2C_STATUS_IC_EN_Pos		(19U)
#define I2C_STATUS_IC_EN_Msk		(0x1UL << I2C_STATUS_IC_EN_Pos)
#define I2C_STATUS_IC_EN    		I2C_STATUS_IC_EN_Msk


#define I2C_STATUS_IC_CURRENT_SRC_EN_Pos		(20U)
#define I2C_STATUS_IC_CURRENT_SRC_EN_Msk		(0x1UL << I2C_STATUS_IC_CURRENT_SRC_EN_Pos)
#define I2C_STATUS_IC_CURRENT_SRC_EN    		I2C_STATUS_IC_CURRENT_SRC_EN_Msk


/****************************** Bit definition for WDT_MCPU_SPEED_UP register ********************************/

#define WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Pos		(0U)
#define WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Msk		(0x1UL << WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Pos)
#define WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP    		WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Msk


/****************************** Bit definition for GBE0_PWR_CTRL register ********************************/

#define GBE0_PWR_CTRL_GBE0_PWR_CTRL_Pos		(0U)
#define GBE0_PWR_CTRL_GBE0_PWR_CTRL_Msk		(0x7UL << GBE0_PWR_CTRL_GBE0_PWR_CTRL_Pos)
#define GBE0_PWR_CTRL_GBE0_PWR_CTRL    		GBE0_PWR_CTRL_GBE0_PWR_CTRL_Msk


/****************************** Bit definition for GBE1_PWR_CTRL register ********************************/

#define GBE1_PWR_CTRL_GBE1_PWR_CTRL_Pos		(0U)
#define GBE1_PWR_CTRL_GBE1_PWR_CTRL_Msk		(0x7UL << GBE1_PWR_CTRL_GBE1_PWR_CTRL_Pos)
#define GBE1_PWR_CTRL_GBE1_PWR_CTRL    		GBE1_PWR_CTRL_GBE1_PWR_CTRL_Msk


/****************************** Bit definition for MCPU_L2_SRAM_DEEPSLEEP register ********************************/

#define MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Pos		(0U)
#define MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Msk		(0xffffffUL << MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Pos)
#define MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP    		MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Msk


/****************************** Bit definition for MCPU_L2_SRAM_POWERGATE register ********************************/

#define MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Pos		(0U)
#define MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Msk		(0xffffffUL << MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Pos)
#define MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE    		MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Msk


/****************************** Bit definition for MCPU_HARTID register ********************************/

#define MCPU_HARTID_MCPU_HARTID_Pos		(0U)
#define MCPU_HARTID_MCPU_HARTID_Msk		(0xffffffffUL << MCPU_HARTID_MCPU_HARTID_Pos)
#define MCPU_HARTID_MCPU_HARTID    		MCPU_HARTID_MCPU_HARTID_Msk


/****************************** Bit definition for MCPU_IO_BASE_ADDR register ********************************/

#define MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Pos		(0U)
#define MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Msk		(0xffffffffUL << MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Pos)
#define MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR    		MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Msk


/****************************** Bit definition for MCPU_MEM_BASE_ADDR register ********************************/

#define MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Pos		(0U)
#define MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Msk		(0xffffffffUL << MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Pos)
#define MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR    		MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Msk


/****************************** Bit definition for MCPU_ICG_DIS register ********************************/

#define MCPU_ICG_DIS_MCPU_ICG_DIS_Pos		(0U)
#define MCPU_ICG_DIS_MCPU_ICG_DIS_Msk		(0x3UL << MCPU_ICG_DIS_MCPU_ICG_DIS_Pos)
#define MCPU_ICG_DIS_MCPU_ICG_DIS    		MCPU_ICG_DIS_MCPU_ICG_DIS_Msk


/****************************** Bit definition for MCPU_CLK_DIS register ********************************/

#define MCPU_CLK_DIS_MCPU_CLK_DIS_Pos		(0U)
#define MCPU_CLK_DIS_MCPU_CLK_DIS_Msk		(0x3UL << MCPU_CLK_DIS_MCPU_CLK_DIS_Pos)
#define MCPU_CLK_DIS_MCPU_CLK_DIS    		MCPU_CLK_DIS_MCPU_CLK_DIS_Msk


/****************************** Bit definition for MCPU_RST_CORE_PC register ********************************/

#define MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Pos		(0U)
#define MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Msk		(0xffffffffUL << MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Pos)
#define MCPU_RST_CORE_PC_MCPU_RST_CORE_PC    		MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Msk


/****************************** Bit definition for DTCM_DEEPSLEEP register ********************************/

#define DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Pos		(0U)
#define DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Msk		(0x1UL << DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Pos)
#define DTCM_DEEPSLEEP_DTCM_DEEPSLEEP    		DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Msk


/****************************** Bit definition for DTCM_POWERGATE register ********************************/

#define DTCM_POWERGATE_DTCM_POWERGATE_Pos		(0U)
#define DTCM_POWERGATE_DTCM_POWERGATE_Msk		(0x1UL << DTCM_POWERGATE_DTCM_POWERGATE_Pos)
#define DTCM_POWERGATE_DTCM_POWERGATE    		DTCM_POWERGATE_DTCM_POWERGATE_Msk


/****************************** Bit definition for ITCM_DEEPSLEEP register ********************************/

#define ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Pos		(0U)
#define ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Msk		(0x1UL << ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Pos)
#define ITCM_DEEPSLEEP_ITCM_DEEPSLEEP    		ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Msk


/****************************** Bit definition for ITCM_POWERGATE register ********************************/

#define ITCM_POWERGATE_ITCM_POWERGATE_Pos		(0U)
#define ITCM_POWERGATE_ITCM_POWERGATE_Msk		(0x1UL << ITCM_POWERGATE_ITCM_POWERGATE_Pos)
#define ITCM_POWERGATE_ITCM_POWERGATE    		ITCM_POWERGATE_ITCM_POWERGATE_Msk


/****************************** Bit definition for MISC_DEEPSLEEP register ********************************/

#define MISC_DEEPSLEEP_MISC_DEEPSLEEP_Pos		(0U)
#define MISC_DEEPSLEEP_MISC_DEEPSLEEP_Msk		(0x1UL << MISC_DEEPSLEEP_MISC_DEEPSLEEP_Pos)
#define MISC_DEEPSLEEP_MISC_DEEPSLEEP    		MISC_DEEPSLEEP_MISC_DEEPSLEEP_Msk


/****************************** Bit definition for MISC_POWERGATE register ********************************/

#define MISC_POWERGATE_MISC_POWERGATE_Pos		(0U)
#define MISC_POWERGATE_MISC_POWERGATE_Msk		(0x1UL << MISC_POWERGATE_MISC_POWERGATE_Pos)
#define MISC_POWERGATE_MISC_POWERGATE    		MISC_POWERGATE_MISC_POWERGATE_Msk


/****************************** Bit definition for JTAG_SEL register ********************************/

#define JTAG_SEL_JTAG_SEL_Pos		(0U)
#define JTAG_SEL_JTAG_SEL_Msk		(0x3UL << JTAG_SEL_JTAG_SEL_Pos)
#define JTAG_SEL_JTAG_SEL    		JTAG_SEL_JTAG_SEL_Msk


#define JTAG_SEL_ACPU_JTAG_SEL_CORE_Pos		(16U)
#define JTAG_SEL_ACPU_JTAG_SEL_CORE_Msk		(0xfUL << JTAG_SEL_ACPU_JTAG_SEL_CORE_Pos)
#define JTAG_SEL_ACPU_JTAG_SEL_CORE    		JTAG_SEL_ACPU_JTAG_SEL_CORE_Msk


/****************************** Bit definition for EXT_ADDR register ********************************/

#define EXT_ADDR_EXT_ADDR_Pos		(0U)
#define EXT_ADDR_EXT_ADDR_Msk		(0xffffffUL << EXT_ADDR_EXT_ADDR_Pos)
#define EXT_ADDR_EXT_ADDR    		EXT_ADDR_EXT_ADDR_Msk


/****************************** Bit definition for SW_RST_N_MCPU register ********************************/

#define SW_RST_N_MCPU_SW_RST_N_MCPU_Pos		(0U)
#define SW_RST_N_MCPU_SW_RST_N_MCPU_Msk		(0x1UL << SW_RST_N_MCPU_SW_RST_N_MCPU_Pos)
#define SW_RST_N_MCPU_SW_RST_N_MCPU    		SW_RST_N_MCPU_SW_RST_N_MCPU_Msk


/****************************** Inline function for SW_RST_CONTROL register ********************************/

static inline void set_sw_rst_control_sw_rst_n_wdt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_WDT, VAL << SW_RST_CONTROL_SW_RST_N_WDT_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_wdt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_WDT) >> SW_RST_CONTROL_SW_RST_N_WDT_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_mbox(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MBOX, VAL << SW_RST_CONTROL_SW_RST_N_MBOX_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_mbox(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MBOX) >> SW_RST_CONTROL_SW_RST_N_MBOX_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_boot_ssi(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_BOOT_SSI, VAL << SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_boot_ssi(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_BOOT_SSI) >> SW_RST_CONTROL_SW_RST_N_BOOT_SSI_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_gpssi(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GPSSI, VAL << SW_RST_CONTROL_SW_RST_N_GPSSI_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_gpssi(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GPSSI) >> SW_RST_CONTROL_SW_RST_N_GPSSI_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_i2c(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_I2C, VAL << SW_RST_CONTROL_SW_RST_N_I2C_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_i2c(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_I2C) >> SW_RST_CONTROL_SW_RST_N_I2C_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_uart(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_UART, VAL << SW_RST_CONTROL_SW_RST_N_UART_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_uart(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_UART) >> SW_RST_CONTROL_SW_RST_N_UART_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_usb1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_USB1, VAL << SW_RST_CONTROL_SW_RST_N_USB1_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_usb1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_USB1) >> SW_RST_CONTROL_SW_RST_N_USB1_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_usb0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_USB0, VAL << SW_RST_CONTROL_SW_RST_N_USB0_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_usb0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_USB0) >> SW_RST_CONTROL_SW_RST_N_USB0_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_gmac_1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GMAC_1, VAL << SW_RST_CONTROL_SW_RST_N_GMAC_1_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_gmac_1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GMAC_1) >> SW_RST_CONTROL_SW_RST_N_GMAC_1_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_gmac_0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GMAC_0, VAL << SW_RST_CONTROL_SW_RST_N_GMAC_0_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_gmac_0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_GMAC_0) >> SW_RST_CONTROL_SW_RST_N_GMAC_0_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_men_1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MEN_1, VAL << SW_RST_CONTROL_SW_RST_N_MEN_1_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_men_1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MEN_1) >> SW_RST_CONTROL_SW_RST_N_MEN_1_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_mem_0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MEM_0, VAL << SW_RST_CONTROL_SW_RST_N_MEM_0_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_mem_0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_MEM_0) >> SW_RST_CONTROL_SW_RST_N_MEM_0_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_hs_1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_HS_1, VAL << SW_RST_CONTROL_SW_RST_N_HS_1_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_hs_1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_HS_1) >> SW_RST_CONTROL_SW_RST_N_HS_1_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_hs_0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_HS_0, VAL << SW_RST_CONTROL_SW_RST_N_HS_0_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_hs_0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_HS_0) >> SW_RST_CONTROL_SW_RST_N_HS_0_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_acpu_boot(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_ACPU_BOOT, VAL << SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_acpu_boot(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_ACPU_BOOT) >> SW_RST_CONTROL_SW_RST_N_ACPU_BOOT_Pos);
}

static inline void set_sw_rst_control_sw_rst_n_acpu_core(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_ACPU_CORE, VAL << SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Pos);
}

static inline uint32_t get_sw_rst_control_sw_rst_n_acpu_core(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_CONTROL, SW_RST_CONTROL_SW_RST_N_ACPU_CORE) >> SW_RST_CONTROL_SW_RST_N_ACPU_CORE_Pos);
}

/****************************** Inline function for ACPU_PLL_CTRL_0 register ********************************/

static inline void set_acpu_pll_ctrl_0_acpu_foutpostdiven(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN, VAL << ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_foutpostdiven(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN) >> ACPU_PLL_CTRL_0_ACPU_FOUTPOSTDIVEN_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_fouten(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUTEN, VAL << ACPU_PLL_CTRL_0_ACPU_FOUTEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_fouten(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUTEN) >> ACPU_PLL_CTRL_0_ACPU_FOUTEN_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_fout4phaseen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN, VAL << ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_fout4phaseen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN) >> ACPU_PLL_CTRL_0_ACPU_FOUT4PHASEEN_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_fbdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FBDIV, VAL << ACPU_PLL_CTRL_0_ACPU_FBDIV_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_fbdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_FBDIV) >> ACPU_PLL_CTRL_0_ACPU_FBDIV_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_refdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_REFDIV, VAL << ACPU_PLL_CTRL_0_ACPU_REFDIV_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_refdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_REFDIV) >> ACPU_PLL_CTRL_0_ACPU_REFDIV_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_postdiv2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_POSTDIV2, VAL << ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_postdiv2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_POSTDIV2) >> ACPU_PLL_CTRL_0_ACPU_POSTDIV2_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_postdiv1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_POSTDIV1, VAL << ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_postdiv1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_POSTDIV1) >> ACPU_PLL_CTRL_0_ACPU_POSTDIV1_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_dsmen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_DSMEN, VAL << ACPU_PLL_CTRL_0_ACPU_DSMEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_dsmen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_DSMEN) >> ACPU_PLL_CTRL_0_ACPU_DSMEN_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_dacen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_DACEN, VAL << ACPU_PLL_CTRL_0_ACPU_DACEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_dacen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_DACEN) >> ACPU_PLL_CTRL_0_ACPU_DACEN_Pos);
}

static inline void set_acpu_pll_ctrl_0_acpu_bypass(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_BYPASS, VAL << ACPU_PLL_CTRL_0_ACPU_BYPASS_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_0_acpu_bypass(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_0, ACPU_PLL_CTRL_0_ACPU_BYPASS) >> ACPU_PLL_CTRL_0_ACPU_BYPASS_Pos);
}

/****************************** Inline function for ACPU_PLL_CTRL_1 register ********************************/

static inline void set_acpu_pll_ctrl_1_acpu_frac(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_1, ACPU_PLL_CTRL_1_ACPU_FRAC, VAL << ACPU_PLL_CTRL_1_ACPU_FRAC_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_1_acpu_frac(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_1, ACPU_PLL_CTRL_1_ACPU_FRAC) >> ACPU_PLL_CTRL_1_ACPU_FRAC_Pos);
}

/****************************** Inline function for ACPU_PLL_CTRL_2 register ********************************/

static inline void set_acpu_pll_ctrl_2_acpu_offsetfastcal(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL, VAL << ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_2_acpu_offsetfastcal(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL) >> ACPU_PLL_CTRL_2_ACPU_OFFSETFASTCAL_Pos);
}

static inline void set_acpu_pll_ctrl_2_acpu_offsetcalin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN, VAL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_2_acpu_offsetcalin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN) >> ACPU_PLL_CTRL_2_ACPU_OFFSETCALIN_Pos);
}

static inline void set_acpu_pll_ctrl_2_acpu_offsetcalen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN, VAL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_2_acpu_offsetcalen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN) >> ACPU_PLL_CTRL_2_ACPU_OFFSETCALEN_Pos);
}

static inline void set_acpu_pll_ctrl_2_acpu_offsetcalcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT, VAL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_2_acpu_offsetcalcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT) >> ACPU_PLL_CTRL_2_ACPU_OFFSETCALCNT_Pos);
}

static inline void set_acpu_pll_ctrl_2_acpu_offsetcalbyp(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP, VAL << ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_2_acpu_offsetcalbyp(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_2, ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP) >> ACPU_PLL_CTRL_2_ACPU_OFFSETCALBYP_Pos);
}

/****************************** Inline function for ACPU_PLL_CTRL_3 register ********************************/

static inline void set_acpu_pll_ctrl_3_acpu_test_calin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_TEST_CALIN, VAL << ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_3_acpu_test_calin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_TEST_CALIN) >> ACPU_PLL_CTRL_3_ACPU_TEST_CALIN_Pos);
}

static inline void set_acpu_pll_ctrl_3_acpu_scanrstb(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANRSTB, VAL << ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_3_acpu_scanrstb(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANRSTB) >> ACPU_PLL_CTRL_3_ACPU_SCANRSTB_Pos);
}

static inline void set_acpu_pll_ctrl_3_acpu_scanmode(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANMODE, VAL << ACPU_PLL_CTRL_3_ACPU_SCANMODE_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_3_acpu_scanmode(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANMODE) >> ACPU_PLL_CTRL_3_ACPU_SCANMODE_Pos);
}

static inline void set_acpu_pll_ctrl_3_acpu_scanin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANIN, VAL << ACPU_PLL_CTRL_3_ACPU_SCANIN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_3_acpu_scanin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANIN) >> ACPU_PLL_CTRL_3_ACPU_SCANIN_Pos);
}

static inline void set_acpu_pll_ctrl_3_acpu_scanen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANEN, VAL << ACPU_PLL_CTRL_3_ACPU_SCANEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_3_acpu_scanen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_3, ACPU_PLL_CTRL_3_ACPU_SCANEN) >> ACPU_PLL_CTRL_3_ACPU_SCANEN_Pos);
}

/****************************** Inline function for ACPU_PLL_CTRL_4 register ********************************/

static inline void set_acpu_pll_ctrl_4_acpu_pllen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_4, ACPU_PLL_CTRL_4_ACPU_PLLEN, VAL << ACPU_PLL_CTRL_4_ACPU_PLLEN_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_4_acpu_pllen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_4, ACPU_PLL_CTRL_4_ACPU_PLLEN) >> ACPU_PLL_CTRL_4_ACPU_PLLEN_Pos);
}

static inline void set_acpu_pll_ctrl_4_acpu_pll_change_freq(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_CTRL_4, ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ, VAL << ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Pos);
}

static inline uint32_t get_acpu_pll_ctrl_4_acpu_pll_change_freq(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_CTRL_4, ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ) >> ACPU_PLL_CTRL_4_ACPU_PLL_CHANGE_FREQ_Pos);
}

/****************************** Inline function for HS_PLL_CTRL_0 register ********************************/

static inline void set_hs_pll_ctrl_0_hs_foutpostdiven(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN, VAL << HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_foutpostdiven(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN) >> HS_PLL_CTRL_0_HS_FOUTPOSTDIVEN_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_fouten(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUTEN, VAL << HS_PLL_CTRL_0_HS_FOUTEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_fouten(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUTEN) >> HS_PLL_CTRL_0_HS_FOUTEN_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_fout4phaseen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUT4PHASEEN, VAL << HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_fout4phaseen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FOUT4PHASEEN) >> HS_PLL_CTRL_0_HS_FOUT4PHASEEN_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_fbdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FBDIV, VAL << HS_PLL_CTRL_0_HS_FBDIV_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_fbdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_FBDIV) >> HS_PLL_CTRL_0_HS_FBDIV_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_refdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_REFDIV, VAL << HS_PLL_CTRL_0_HS_REFDIV_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_refdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_REFDIV) >> HS_PLL_CTRL_0_HS_REFDIV_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_postdiv2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_POSTDIV2, VAL << HS_PLL_CTRL_0_HS_POSTDIV2_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_postdiv2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_POSTDIV2) >> HS_PLL_CTRL_0_HS_POSTDIV2_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_postdiv1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_POSTDIV1, VAL << HS_PLL_CTRL_0_HS_POSTDIV1_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_postdiv1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_POSTDIV1) >> HS_PLL_CTRL_0_HS_POSTDIV1_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_dsmen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_DSMEN, VAL << HS_PLL_CTRL_0_HS_DSMEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_dsmen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_DSMEN) >> HS_PLL_CTRL_0_HS_DSMEN_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_dacen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_DACEN, VAL << HS_PLL_CTRL_0_HS_DACEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_dacen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_DACEN) >> HS_PLL_CTRL_0_HS_DACEN_Pos);
}

static inline void set_hs_pll_ctrl_0_hs_bypass(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_BYPASS, VAL << HS_PLL_CTRL_0_HS_BYPASS_Pos);
}

static inline uint32_t get_hs_pll_ctrl_0_hs_bypass(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_0, HS_PLL_CTRL_0_HS_BYPASS) >> HS_PLL_CTRL_0_HS_BYPASS_Pos);
}

/****************************** Inline function for HS_PLL_CTRL_1 register ********************************/

static inline void set_hs_pll_ctrl_1_hs_frac(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_1, HS_PLL_CTRL_1_HS_FRAC, VAL << HS_PLL_CTRL_1_HS_FRAC_Pos);
}

static inline uint32_t get_hs_pll_ctrl_1_hs_frac(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_1, HS_PLL_CTRL_1_HS_FRAC) >> HS_PLL_CTRL_1_HS_FRAC_Pos);
}

/****************************** Inline function for HS_PLL_CTRL_2 register ********************************/

static inline void set_hs_pll_ctrl_2_hs_offsetfastcal(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETFASTCAL, VAL << HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Pos);
}

static inline uint32_t get_hs_pll_ctrl_2_hs_offsetfastcal(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETFASTCAL) >> HS_PLL_CTRL_2_HS_OFFSETFASTCAL_Pos);
}

static inline void set_hs_pll_ctrl_2_hs_offsetcalin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALIN, VAL << HS_PLL_CTRL_2_HS_OFFSETCALIN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_2_hs_offsetcalin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALIN) >> HS_PLL_CTRL_2_HS_OFFSETCALIN_Pos);
}

static inline void set_hs_pll_ctrl_2_hs_offsetcalen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALEN, VAL << HS_PLL_CTRL_2_HS_OFFSETCALEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_2_hs_offsetcalen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALEN) >> HS_PLL_CTRL_2_HS_OFFSETCALEN_Pos);
}

static inline void set_hs_pll_ctrl_2_hs_offsetcalcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALCNT, VAL << HS_PLL_CTRL_2_HS_OFFSETCALCNT_Pos);
}

static inline uint32_t get_hs_pll_ctrl_2_hs_offsetcalcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALCNT) >> HS_PLL_CTRL_2_HS_OFFSETCALCNT_Pos);
}

static inline void set_hs_pll_ctrl_2_hs_offsetcalbyp(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALBYP, VAL << HS_PLL_CTRL_2_HS_OFFSETCALBYP_Pos);
}

static inline uint32_t get_hs_pll_ctrl_2_hs_offsetcalbyp(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_2, HS_PLL_CTRL_2_HS_OFFSETCALBYP) >> HS_PLL_CTRL_2_HS_OFFSETCALBYP_Pos);
}

/****************************** Inline function for HS_PLL_CTRL_3 register ********************************/

static inline void set_hs_pll_ctrl_3_hs_test_calin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_TEST_CALIN, VAL << HS_PLL_CTRL_3_HS_TEST_CALIN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_3_hs_test_calin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_TEST_CALIN) >> HS_PLL_CTRL_3_HS_TEST_CALIN_Pos);
}

static inline void set_hs_pll_ctrl_3_hs_scanrstb(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANRSTB, VAL << HS_PLL_CTRL_3_HS_SCANRSTB_Pos);
}

static inline uint32_t get_hs_pll_ctrl_3_hs_scanrstb(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANRSTB) >> HS_PLL_CTRL_3_HS_SCANRSTB_Pos);
}

static inline void set_hs_pll_ctrl_3_hs_scanmode(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANMODE, VAL << HS_PLL_CTRL_3_HS_SCANMODE_Pos);
}

static inline uint32_t get_hs_pll_ctrl_3_hs_scanmode(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANMODE) >> HS_PLL_CTRL_3_HS_SCANMODE_Pos);
}

static inline void set_hs_pll_ctrl_3_hs_scanin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANIN, VAL << HS_PLL_CTRL_3_HS_SCANIN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_3_hs_scanin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANIN) >> HS_PLL_CTRL_3_HS_SCANIN_Pos);
}

static inline void set_hs_pll_ctrl_3_hs_scanen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANEN, VAL << HS_PLL_CTRL_3_HS_SCANEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_3_hs_scanen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_3, HS_PLL_CTRL_3_HS_SCANEN) >> HS_PLL_CTRL_3_HS_SCANEN_Pos);
}

/****************************** Inline function for HS_PLL_CTRL_4 register ********************************/

static inline void set_hs_pll_ctrl_4_hs_pllen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_4, HS_PLL_CTRL_4_HS_PLLEN, VAL << HS_PLL_CTRL_4_HS_PLLEN_Pos);
}

static inline uint32_t get_hs_pll_ctrl_4_hs_pllen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_4, HS_PLL_CTRL_4_HS_PLLEN) >> HS_PLL_CTRL_4_HS_PLLEN_Pos);
}

static inline void set_hs_pll_ctrl_4_hs_pll_change_freq(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_CTRL_4, HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ, VAL << HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Pos);
}

static inline uint32_t get_hs_pll_ctrl_4_hs_pll_change_freq(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_CTRL_4, HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ) >> HS_PLL_CTRL_4_HS_PLL_CHANGE_FREQ_Pos);
}

/****************************** Inline function for MEMORY_PLL_CTRL_0 register ********************************/

static inline void set_memory_pll_ctrl_0_mem_foutpostdiven(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN, VAL << MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_foutpostdiven(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN) >> MEMORY_PLL_CTRL_0_MEM_FOUTPOSTDIVEN_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_fouten(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUTEN, VAL << MEMORY_PLL_CTRL_0_MEM_FOUTEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_fouten(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUTEN) >> MEMORY_PLL_CTRL_0_MEM_FOUTEN_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_fout4phaseen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN, VAL << MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_fout4phaseen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN) >> MEMORY_PLL_CTRL_0_MEM_FOUT4PHASEEN_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_fbdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FBDIV, VAL << MEMORY_PLL_CTRL_0_MEM_FBDIV_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_fbdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_FBDIV) >> MEMORY_PLL_CTRL_0_MEM_FBDIV_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_refdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_REFDIV, VAL << MEMORY_PLL_CTRL_0_MEM_REFDIV_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_refdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_REFDIV) >> MEMORY_PLL_CTRL_0_MEM_REFDIV_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_postdiv2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_POSTDIV2, VAL << MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_postdiv2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_POSTDIV2) >> MEMORY_PLL_CTRL_0_MEM_POSTDIV2_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_postdiv1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_POSTDIV1, VAL << MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_postdiv1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_POSTDIV1) >> MEMORY_PLL_CTRL_0_MEM_POSTDIV1_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_dsmen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_DSMEN, VAL << MEMORY_PLL_CTRL_0_MEM_DSMEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_dsmen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_DSMEN) >> MEMORY_PLL_CTRL_0_MEM_DSMEN_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_dacen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_DACEN, VAL << MEMORY_PLL_CTRL_0_MEM_DACEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_dacen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_DACEN) >> MEMORY_PLL_CTRL_0_MEM_DACEN_Pos);
}

static inline void set_memory_pll_ctrl_0_mem_bypass(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_BYPASS, VAL << MEMORY_PLL_CTRL_0_MEM_BYPASS_Pos);
}

static inline uint32_t get_memory_pll_ctrl_0_mem_bypass(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_0, MEMORY_PLL_CTRL_0_MEM_BYPASS) >> MEMORY_PLL_CTRL_0_MEM_BYPASS_Pos);
}

/****************************** Inline function for MEMORY_PLL_CTRL_1 register ********************************/

static inline void set_memory_pll_ctrl_1_mem_frac(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_1, MEMORY_PLL_CTRL_1_MEM_FRAC, VAL << MEMORY_PLL_CTRL_1_MEM_FRAC_Pos);
}

static inline uint32_t get_memory_pll_ctrl_1_mem_frac(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_1, MEMORY_PLL_CTRL_1_MEM_FRAC) >> MEMORY_PLL_CTRL_1_MEM_FRAC_Pos);
}

/****************************** Inline function for MEMORY_PLL_CTRL_2 register ********************************/

static inline void set_memory_pll_ctrl_2_mem_offsetfastcal(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL, VAL << MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Pos);
}

static inline uint32_t get_memory_pll_ctrl_2_mem_offsetfastcal(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL) >> MEMORY_PLL_CTRL_2_MEM_OFFSETFASTCAL_Pos);
}

static inline void set_memory_pll_ctrl_2_mem_offsetcalin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN, VAL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_2_mem_offsetcalin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN) >> MEMORY_PLL_CTRL_2_MEM_OFFSETCALIN_Pos);
}

static inline void set_memory_pll_ctrl_2_mem_offsetcalen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN, VAL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_2_mem_offsetcalen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN) >> MEMORY_PLL_CTRL_2_MEM_OFFSETCALEN_Pos);
}

static inline void set_memory_pll_ctrl_2_mem_offsetcalcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT, VAL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Pos);
}

static inline uint32_t get_memory_pll_ctrl_2_mem_offsetcalcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT) >> MEMORY_PLL_CTRL_2_MEM_OFFSETCALCNT_Pos);
}

static inline void set_memory_pll_ctrl_2_mem_offsetcalbyp(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP, VAL << MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Pos);
}

static inline uint32_t get_memory_pll_ctrl_2_mem_offsetcalbyp(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_2, MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP) >> MEMORY_PLL_CTRL_2_MEM_OFFSETCALBYP_Pos);
}

/****************************** Inline function for MEMORY_PLL_CTRL_3 register ********************************/

static inline void set_memory_pll_ctrl_3_mem_test_calin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_TEST_CALIN, VAL << MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_3_mem_test_calin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_TEST_CALIN) >> MEMORY_PLL_CTRL_3_MEM_TEST_CALIN_Pos);
}

static inline void set_memory_pll_ctrl_3_mem_scanrstb(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANRSTB, VAL << MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Pos);
}

static inline uint32_t get_memory_pll_ctrl_3_mem_scanrstb(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANRSTB) >> MEMORY_PLL_CTRL_3_MEM_SCANRSTB_Pos);
}

static inline void set_memory_pll_ctrl_3_mem_scanmode(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANMODE, VAL << MEMORY_PLL_CTRL_3_MEM_SCANMODE_Pos);
}

static inline uint32_t get_memory_pll_ctrl_3_mem_scanmode(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANMODE) >> MEMORY_PLL_CTRL_3_MEM_SCANMODE_Pos);
}

static inline void set_memory_pll_ctrl_3_mem_scanin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANIN, VAL << MEMORY_PLL_CTRL_3_MEM_SCANIN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_3_mem_scanin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANIN) >> MEMORY_PLL_CTRL_3_MEM_SCANIN_Pos);
}

static inline void set_memory_pll_ctrl_3_mem_scanen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANEN, VAL << MEMORY_PLL_CTRL_3_MEM_SCANEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_3_mem_scanen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_3, MEMORY_PLL_CTRL_3_MEM_SCANEN) >> MEMORY_PLL_CTRL_3_MEM_SCANEN_Pos);
}

/****************************** Inline function for MEMORY_PLL_CTRL_4 register ********************************/

static inline void set_memory_pll_ctrl_4_mem_pllen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_4, MEMORY_PLL_CTRL_4_MEM_PLLEN, VAL << MEMORY_PLL_CTRL_4_MEM_PLLEN_Pos);
}

static inline uint32_t get_memory_pll_ctrl_4_mem_pllen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_4, MEMORY_PLL_CTRL_4_MEM_PLLEN) >> MEMORY_PLL_CTRL_4_MEM_PLLEN_Pos);
}

static inline void set_memory_pll_ctrl_4_mem_pll_change_freq(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEMORY_PLL_CTRL_4, MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ, VAL << MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Pos);
}

static inline uint32_t get_memory_pll_ctrl_4_mem_pll_change_freq(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEMORY_PLL_CTRL_4, MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ) >> MEMORY_PLL_CTRL_4_MEM_PLL_CHANGE_FREQ_Pos);
}

/****************************** Inline function for MCPU_PLL_CTRL_0 register ********************************/

static inline void set_mcpu_pll_ctrl_0_mcpu_foutpostdiven(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN, VAL << MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_foutpostdiven(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN) >> MCPU_PLL_CTRL_0_MCPU_FOUTPOSTDIVEN_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_fouten(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUTEN, VAL << MCPU_PLL_CTRL_0_MCPU_FOUTEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_fouten(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUTEN) >> MCPU_PLL_CTRL_0_MCPU_FOUTEN_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_fout4phaseen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN, VAL << MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_fout4phaseen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN) >> MCPU_PLL_CTRL_0_MCPU_FOUT4PHASEEN_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_fbdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FBDIV, VAL << MCPU_PLL_CTRL_0_MCPU_FBDIV_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_fbdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_FBDIV) >> MCPU_PLL_CTRL_0_MCPU_FBDIV_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_refdiv(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_REFDIV, VAL << MCPU_PLL_CTRL_0_MCPU_REFDIV_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_refdiv(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_REFDIV) >> MCPU_PLL_CTRL_0_MCPU_REFDIV_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_postdiv2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_POSTDIV2, VAL << MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_postdiv2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_POSTDIV2) >> MCPU_PLL_CTRL_0_MCPU_POSTDIV2_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_postdiv1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_POSTDIV1, VAL << MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_postdiv1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_POSTDIV1) >> MCPU_PLL_CTRL_0_MCPU_POSTDIV1_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_dsmen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_DSMEN, VAL << MCPU_PLL_CTRL_0_MCPU_DSMEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_dsmen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_DSMEN) >> MCPU_PLL_CTRL_0_MCPU_DSMEN_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_dacen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_DACEN, VAL << MCPU_PLL_CTRL_0_MCPU_DACEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_dacen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_DACEN) >> MCPU_PLL_CTRL_0_MCPU_DACEN_Pos);
}

static inline void set_mcpu_pll_ctrl_0_mcpu_bypass(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_BYPASS, VAL << MCPU_PLL_CTRL_0_MCPU_BYPASS_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_0_mcpu_bypass(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_0, MCPU_PLL_CTRL_0_MCPU_BYPASS) >> MCPU_PLL_CTRL_0_MCPU_BYPASS_Pos);
}

/****************************** Inline function for MCPU_PLL_CTRL_1 register ********************************/

static inline void set_mcpu_pll_ctrl_1_mcpu_frac(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_1, MCPU_PLL_CTRL_1_MCPU_FRAC, VAL << MCPU_PLL_CTRL_1_MCPU_FRAC_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_1_mcpu_frac(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_1, MCPU_PLL_CTRL_1_MCPU_FRAC) >> MCPU_PLL_CTRL_1_MCPU_FRAC_Pos);
}

/****************************** Inline function for MCPU_PLL_CTRL_2 register ********************************/

static inline void set_mcpu_pll_ctrl_2_mcpu_offsetfastcal(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL, VAL << MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_2_mcpu_offsetfastcal(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL) >> MCPU_PLL_CTRL_2_MCPU_OFFSETFASTCAL_Pos);
}

static inline void set_mcpu_pll_ctrl_2_mcpu_offsetcalin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN, VAL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_2_mcpu_offsetcalin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN) >> MCPU_PLL_CTRL_2_MCPU_OFFSETCALIN_Pos);
}

static inline void set_mcpu_pll_ctrl_2_mcpu_offsetcalen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN, VAL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_2_mcpu_offsetcalen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN) >> MCPU_PLL_CTRL_2_MCPU_OFFSETCALEN_Pos);
}

static inline void set_mcpu_pll_ctrl_2_mcpu_offsetcalcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT, VAL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_2_mcpu_offsetcalcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT) >> MCPU_PLL_CTRL_2_MCPU_OFFSETCALCNT_Pos);
}

static inline void set_mcpu_pll_ctrl_2_mcpu_offsetcalbyp(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP, VAL << MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_2_mcpu_offsetcalbyp(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_2, MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP) >> MCPU_PLL_CTRL_2_MCPU_OFFSETCALBYP_Pos);
}

/****************************** Inline function for MCPU_PLL_CTRL_3 register ********************************/

static inline void set_mcpu_pll_ctrl_3_mcpu_test_calin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_TEST_CALIN, VAL << MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_3_mcpu_test_calin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_TEST_CALIN) >> MCPU_PLL_CTRL_3_MCPU_TEST_CALIN_Pos);
}

static inline void set_mcpu_pll_ctrl_3_mcpu_scanrstb(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANRSTB, VAL << MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_3_mcpu_scanrstb(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANRSTB) >> MCPU_PLL_CTRL_3_MCPU_SCANRSTB_Pos);
}

static inline void set_mcpu_pll_ctrl_3_mcpu_scanmode(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANMODE, VAL << MCPU_PLL_CTRL_3_MCPU_SCANMODE_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_3_mcpu_scanmode(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANMODE) >> MCPU_PLL_CTRL_3_MCPU_SCANMODE_Pos);
}

static inline void set_mcpu_pll_ctrl_3_mcpu_scanin(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANIN, VAL << MCPU_PLL_CTRL_3_MCPU_SCANIN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_3_mcpu_scanin(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANIN) >> MCPU_PLL_CTRL_3_MCPU_SCANIN_Pos);
}

static inline void set_mcpu_pll_ctrl_3_mcpu_scanen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANEN, VAL << MCPU_PLL_CTRL_3_MCPU_SCANEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_3_mcpu_scanen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_3, MCPU_PLL_CTRL_3_MCPU_SCANEN) >> MCPU_PLL_CTRL_3_MCPU_SCANEN_Pos);
}

/****************************** Inline function for MCPU_PLL_CTRL_4 register ********************************/

static inline void set_mcpu_pll_ctrl_4_mcpu_pllen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_4, MCPU_PLL_CTRL_4_MCPU_PLLEN, VAL << MCPU_PLL_CTRL_4_MCPU_PLLEN_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_4_mcpu_pllen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_4, MCPU_PLL_CTRL_4_MCPU_PLLEN) >> MCPU_PLL_CTRL_4_MCPU_PLLEN_Pos);
}

static inline void set_mcpu_pll_ctrl_4_mcpu_pll_change_freq(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_CTRL_4, MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ, VAL << MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Pos);
}

static inline uint32_t get_mcpu_pll_ctrl_4_mcpu_pll_change_freq(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_CTRL_4, MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ) >> MCPU_PLL_CTRL_4_MCPU_PLL_CHANGE_FREQ_Pos);
}

/****************************** Inline function for PERIPH_DIV register ********************************/

static inline void set_periph_div_div(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PERIPH_DIV, PERIPH_DIV_DIV, VAL << PERIPH_DIV_DIV_Pos);
}

static inline uint32_t get_periph_div_div(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PERIPH_DIV, PERIPH_DIV_DIV) >> PERIPH_DIV_DIV_Pos);
}

/****************************** Inline function for GATING_CONTROL register ********************************/

static inline void set_gating_control_cg_mem(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GATING_CONTROL, GATING_CONTROL_CG_MEM, VAL << GATING_CONTROL_CG_MEM_Pos);
}

static inline uint32_t get_gating_control_cg_mem(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GATING_CONTROL, GATING_CONTROL_CG_MEM) >> GATING_CONTROL_CG_MEM_Pos);
}

static inline void set_gating_control_cg_hs(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GATING_CONTROL, GATING_CONTROL_CG_HS, VAL << GATING_CONTROL_CG_HS_Pos);
}

static inline uint32_t get_gating_control_cg_hs(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GATING_CONTROL, GATING_CONTROL_CG_HS) >> GATING_CONTROL_CG_HS_Pos);
}

static inline void set_gating_control_cg_acpu(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GATING_CONTROL, GATING_CONTROL_CG_ACPU, VAL << GATING_CONTROL_CG_ACPU_Pos);
}

static inline uint32_t get_gating_control_cg_acpu(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GATING_CONTROL, GATING_CONTROL_CG_ACPU) >> GATING_CONTROL_CG_ACPU_Pos);
}

/****************************** Inline function for BOOTSTRAP_STATUS register ********************************/

static inline void set_bootstrap_status_bypass_clock_status(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS, VAL << BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Pos);
}

static inline uint32_t get_bootstrap_status_bypass_clock_status(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS) >> BOOTSTRAP_STATUS_BYPASS_CLOCK_STATUS_Pos);
}

static inline void set_bootstrap_status_bootm(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_BOOTM, VAL << BOOTSTRAP_STATUS_BOOTM_Pos);
}

static inline uint32_t get_bootstrap_status_bootm(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_BOOTM) >> BOOTSTRAP_STATUS_BOOTM_Pos);
}

static inline void set_bootstrap_status_mcpu_sw_rst_status(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS, VAL << BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Pos);
}

static inline uint32_t get_bootstrap_status_mcpu_sw_rst_status(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS) >> BOOTSTRAP_STATUS_MCPU_SW_RST_STATUS_Pos);
}

static inline void set_bootstrap_status_mcpu_lock_rst_status(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS, VAL << BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Pos);
}

static inline uint32_t get_bootstrap_status_mcpu_lock_rst_status(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS) >> BOOTSTRAP_STATUS_MCPU_LOCK_RST_STATUS_Pos);
}

static inline void set_bootstrap_status_mcpu_wdt_rst_status(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS, VAL << BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Pos);
}

static inline uint32_t get_bootstrap_status_mcpu_wdt_rst_status(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS) >> BOOTSTRAP_STATUS_MCPU_WDT_RST_STATUS_Pos);
}

static inline void set_bootstrap_status_mcpu_dm_rst_status(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS, VAL << BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Pos);
}

static inline uint32_t get_bootstrap_status_mcpu_dm_rst_status(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS) >> BOOTSTRAP_STATUS_MCPU_DM_RST_STATUS_Pos);
}

static inline void set_bootstrap_status_sw_control(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_SW_CONTROL, VAL << BOOTSTRAP_STATUS_SW_CONTROL_Pos);
}

static inline uint32_t get_bootstrap_status_sw_control(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOTSTRAP_STATUS, BOOTSTRAP_STATUS_SW_CONTROL) >> BOOTSTRAP_STATUS_SW_CONTROL_Pos);
}

/****************************** Inline function for ACPU_PLL_STATUS register ********************************/

static inline void set_acpu_pll_status_acpu_lock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_LOCK, VAL << ACPU_PLL_STATUS_ACPU_LOCK_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_lock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_LOCK) >> ACPU_PLL_STATUS_ACPU_LOCK_Pos);
}

static inline void set_acpu_pll_status_acpu_offsetcallock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK, VAL << ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_offsetcallock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK) >> ACPU_PLL_STATUS_ACPU_OFFSETCALLOCK_Pos);
}

static inline void set_acpu_pll_status_acpu_offsetcallockcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT, VAL << ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_offsetcallockcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT) >> ACPU_PLL_STATUS_ACPU_OFFSETCALLOCKCNT_Pos);
}

static inline void set_acpu_pll_status_acpu_offsetcalout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALOUT, VAL << ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_offsetcalout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_OFFSETCALOUT) >> ACPU_PLL_STATUS_ACPU_OFFSETCALOUT_Pos);
}

static inline void set_acpu_pll_status_acpu_scanout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_SCANOUT, VAL << ACPU_PLL_STATUS_ACPU_SCANOUT_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_scanout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_SCANOUT) >> ACPU_PLL_STATUS_ACPU_SCANOUT_Pos);
}

static inline void set_acpu_pll_status_acpu_test_calout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_TEST_CALOUT, VAL << ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Pos);
}

static inline uint32_t get_acpu_pll_status_acpu_test_calout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PLL_STATUS, ACPU_PLL_STATUS_ACPU_TEST_CALOUT) >> ACPU_PLL_STATUS_ACPU_TEST_CALOUT_Pos);
}

/****************************** Inline function for HS_PLL_STATUS register ********************************/

static inline void set_hs_pll_status_lock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_LOCK, VAL << HS_PLL_STATUS_LOCK_Pos);
}

static inline uint32_t get_hs_pll_status_lock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_LOCK) >> HS_PLL_STATUS_LOCK_Pos);
}

static inline void set_hs_pll_status_hs_offsetcallock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALLOCK, VAL << HS_PLL_STATUS_HS_OFFSETCALLOCK_Pos);
}

static inline uint32_t get_hs_pll_status_hs_offsetcallock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALLOCK) >> HS_PLL_STATUS_HS_OFFSETCALLOCK_Pos);
}

static inline void set_hs_pll_status_hs_offsetcallockcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALLOCKCNT, VAL << HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Pos);
}

static inline uint32_t get_hs_pll_status_hs_offsetcallockcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALLOCKCNT) >> HS_PLL_STATUS_HS_OFFSETCALLOCKCNT_Pos);
}

static inline void set_hs_pll_status_hs_offsetcalout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALOUT, VAL << HS_PLL_STATUS_HS_OFFSETCALOUT_Pos);
}

static inline uint32_t get_hs_pll_status_hs_offsetcalout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_OFFSETCALOUT) >> HS_PLL_STATUS_HS_OFFSETCALOUT_Pos);
}

static inline void set_hs_pll_status_hs_scanout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_SCANOUT, VAL << HS_PLL_STATUS_HS_SCANOUT_Pos);
}

static inline uint32_t get_hs_pll_status_hs_scanout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_SCANOUT) >> HS_PLL_STATUS_HS_SCANOUT_Pos);
}

static inline void set_hs_pll_status_hs_test_calout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_TEST_CALOUT, VAL << HS_PLL_STATUS_HS_TEST_CALOUT_Pos);
}

static inline uint32_t get_hs_pll_status_hs_test_calout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HS_PLL_STATUS, HS_PLL_STATUS_HS_TEST_CALOUT) >> HS_PLL_STATUS_HS_TEST_CALOUT_Pos);
}

/****************************** Inline function for MEM_PLL_STATUS register ********************************/

static inline void set_mem_pll_status_mem_lock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_LOCK, VAL << MEM_PLL_STATUS_MEM_LOCK_Pos);
}

static inline uint32_t get_mem_pll_status_mem_lock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_LOCK) >> MEM_PLL_STATUS_MEM_LOCK_Pos);
}

static inline void set_mem_pll_status_mem_offsetcallock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALLOCK, VAL << MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Pos);
}

static inline uint32_t get_mem_pll_status_mem_offsetcallock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALLOCK) >> MEM_PLL_STATUS_MEM_OFFSETCALLOCK_Pos);
}

static inline void set_mem_pll_status_mem_offsetcallockcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT, VAL << MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Pos);
}

static inline uint32_t get_mem_pll_status_mem_offsetcallockcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT) >> MEM_PLL_STATUS_MEM_OFFSETCALLOCKCNT_Pos);
}

static inline void set_mem_pll_status_mem_offsetcalout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALOUT, VAL << MEM_PLL_STATUS_MEM_OFFSETCALOUT_Pos);
}

static inline uint32_t get_mem_pll_status_mem_offsetcalout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_OFFSETCALOUT) >> MEM_PLL_STATUS_MEM_OFFSETCALOUT_Pos);
}

static inline void set_mem_pll_status_mem_scanout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_SCANOUT, VAL << MEM_PLL_STATUS_MEM_SCANOUT_Pos);
}

static inline uint32_t get_mem_pll_status_mem_scanout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_SCANOUT) >> MEM_PLL_STATUS_MEM_SCANOUT_Pos);
}

static inline void set_mem_pll_status_mem_test_calout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_TEST_CALOUT, VAL << MEM_PLL_STATUS_MEM_TEST_CALOUT_Pos);
}

static inline uint32_t get_mem_pll_status_mem_test_calout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MEM_PLL_STATUS, MEM_PLL_STATUS_MEM_TEST_CALOUT) >> MEM_PLL_STATUS_MEM_TEST_CALOUT_Pos);
}

/****************************** Inline function for MCPU_PLL_STATUS register ********************************/

static inline void set_mcpu_pll_status_mcpu_lock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_LOCK, VAL << MCPU_PLL_STATUS_MCPU_LOCK_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_lock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_LOCK) >> MCPU_PLL_STATUS_MCPU_LOCK_Pos);
}

static inline void set_mcpu_pll_status_mcpu_offsetcallock(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK, VAL << MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_offsetcallock(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK) >> MCPU_PLL_STATUS_MCPU_OFFSETCALLOCK_Pos);
}

static inline void set_mcpu_pll_status_mcpu_offsetcallockcnt(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT, VAL << MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_offsetcallockcnt(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT) >> MCPU_PLL_STATUS_MCPU_OFFSETCALLOCKCNT_Pos);
}

static inline void set_mcpu_pll_status_mcpu_offsetcalout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALOUT, VAL << MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_offsetcalout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_OFFSETCALOUT) >> MCPU_PLL_STATUS_MCPU_OFFSETCALOUT_Pos);
}

static inline void set_mcpu_pll_status_mcpu_scanout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_SCANOUT, VAL << MCPU_PLL_STATUS_MCPU_SCANOUT_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_scanout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_SCANOUT) >> MCPU_PLL_STATUS_MCPU_SCANOUT_Pos);
}

static inline void set_mcpu_pll_status_mcpu_test_calout(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_TEST_CALOUT, VAL << MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Pos);
}

static inline uint32_t get_mcpu_pll_status_mcpu_test_calout(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_PLL_STATUS, MCPU_PLL_STATUS_MCPU_TEST_CALOUT) >> MCPU_PLL_STATUS_MCPU_TEST_CALOUT_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_0 register ********************************/

static inline void set_irq_mask_map_control_0_irq_mask_0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_0, IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0, VAL << IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Pos);
}

static inline uint32_t get_irq_mask_map_control_0_irq_mask_0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_0, IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0) >> IRQ_MASK_MAP_CONTROL_0_IRQ_MASK_0_Pos);
}

static inline void set_irq_mask_map_control_0_irq_map_0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_0, IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0, VAL << IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Pos);
}

static inline uint32_t get_irq_mask_map_control_0_irq_map_0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_0, IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0) >> IRQ_MASK_MAP_CONTROL_0_IRQ_MAP_0_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_1 register ********************************/

static inline void set_irq_mask_map_control_1_irq_mask_1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_1, IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1, VAL << IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Pos);
}

static inline uint32_t get_irq_mask_map_control_1_irq_mask_1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_1, IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1) >> IRQ_MASK_MAP_CONTROL_1_IRQ_MASK_1_Pos);
}

static inline void set_irq_mask_map_control_1_irq_map_1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_1, IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1, VAL << IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Pos);
}

static inline uint32_t get_irq_mask_map_control_1_irq_map_1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_1, IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1) >> IRQ_MASK_MAP_CONTROL_1_IRQ_MAP_1_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_2 register ********************************/

static inline void set_irq_mask_map_control_2_irq_mask_2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_2, IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2, VAL << IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Pos);
}

static inline uint32_t get_irq_mask_map_control_2_irq_mask_2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_2, IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2) >> IRQ_MASK_MAP_CONTROL_2_IRQ_MASK_2_Pos);
}

static inline void set_irq_mask_map_control_2_irq_map_2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_2, IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2, VAL << IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Pos);
}

static inline uint32_t get_irq_mask_map_control_2_irq_map_2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_2, IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2) >> IRQ_MASK_MAP_CONTROL_2_IRQ_MAP_2_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_3 register ********************************/

static inline void set_irq_mask_map_control_3_irq_mask_3(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_3, IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3, VAL << IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Pos);
}

static inline uint32_t get_irq_mask_map_control_3_irq_mask_3(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_3, IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3) >> IRQ_MASK_MAP_CONTROL_3_IRQ_MASK_3_Pos);
}

static inline void set_irq_mask_map_control_3_irq_map_3(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_3, IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3, VAL << IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Pos);
}

static inline uint32_t get_irq_mask_map_control_3_irq_map_3(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_3, IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3) >> IRQ_MASK_MAP_CONTROL_3_IRQ_MAP_3_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_4 register ********************************/

static inline void set_irq_mask_map_control_4_irq_mask_4(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_4, IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4, VAL << IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Pos);
}

static inline uint32_t get_irq_mask_map_control_4_irq_mask_4(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_4, IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4) >> IRQ_MASK_MAP_CONTROL_4_IRQ_MASK_4_Pos);
}

static inline void set_irq_mask_map_control_4_irq_map_4(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_4, IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4, VAL << IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Pos);
}

static inline uint32_t get_irq_mask_map_control_4_irq_map_4(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_4, IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4) >> IRQ_MASK_MAP_CONTROL_4_IRQ_MAP_4_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_5 register ********************************/

static inline void set_irq_mask_map_control_5_irq_mask_5(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_5, IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5, VAL << IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Pos);
}

static inline uint32_t get_irq_mask_map_control_5_irq_mask_5(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_5, IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5) >> IRQ_MASK_MAP_CONTROL_5_IRQ_MASK_5_Pos);
}

static inline void set_irq_mask_map_control_5_irq_map_5(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_5, IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5, VAL << IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Pos);
}

static inline uint32_t get_irq_mask_map_control_5_irq_map_5(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_5, IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5) >> IRQ_MASK_MAP_CONTROL_5_IRQ_MAP_5_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_6 register ********************************/

static inline void set_irq_mask_map_control_6_irq_mask_6(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_6, IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6, VAL << IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Pos);
}

static inline uint32_t get_irq_mask_map_control_6_irq_mask_6(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_6, IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6) >> IRQ_MASK_MAP_CONTROL_6_IRQ_MASK_6_Pos);
}

static inline void set_irq_mask_map_control_6_irq_map_6(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_6, IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6, VAL << IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Pos);
}

static inline uint32_t get_irq_mask_map_control_6_irq_map_6(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_6, IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6) >> IRQ_MASK_MAP_CONTROL_6_IRQ_MAP_6_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_7 register ********************************/

static inline void set_irq_mask_map_control_7_irq_mask_7(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_7, IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7, VAL << IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Pos);
}

static inline uint32_t get_irq_mask_map_control_7_irq_mask_7(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_7, IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7) >> IRQ_MASK_MAP_CONTROL_7_IRQ_MASK_7_Pos);
}

static inline void set_irq_mask_map_control_7_irq_map_7(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_7, IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7, VAL << IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Pos);
}

static inline uint32_t get_irq_mask_map_control_7_irq_map_7(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_7, IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7) >> IRQ_MASK_MAP_CONTROL_7_IRQ_MAP_7_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_8 register ********************************/

static inline void set_irq_mask_map_control_8_irq_mask_8(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_8, IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8, VAL << IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Pos);
}

static inline uint32_t get_irq_mask_map_control_8_irq_mask_8(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_8, IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8) >> IRQ_MASK_MAP_CONTROL_8_IRQ_MASK_8_Pos);
}

static inline void set_irq_mask_map_control_8_irq_map_8(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_8, IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8, VAL << IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Pos);
}

static inline uint32_t get_irq_mask_map_control_8_irq_map_8(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_8, IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8) >> IRQ_MASK_MAP_CONTROL_8_IRQ_MAP_8_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_9 register ********************************/

static inline void set_irq_mask_map_control_9_irq_mask_9(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_9, IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9, VAL << IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Pos);
}

static inline uint32_t get_irq_mask_map_control_9_irq_mask_9(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_9, IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9) >> IRQ_MASK_MAP_CONTROL_9_IRQ_MASK_9_Pos);
}

static inline void set_irq_mask_map_control_9_irq_map_9(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_9, IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9, VAL << IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Pos);
}

static inline uint32_t get_irq_mask_map_control_9_irq_map_9(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_9, IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9) >> IRQ_MASK_MAP_CONTROL_9_IRQ_MAP_9_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_10 register ********************************/

static inline void set_irq_mask_map_control_10_irq_mask_10(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_10, IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10, VAL << IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Pos);
}

static inline uint32_t get_irq_mask_map_control_10_irq_mask_10(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_10, IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10) >> IRQ_MASK_MAP_CONTROL_10_IRQ_MASK_10_Pos);
}

static inline void set_irq_mask_map_control_10_irq_map_10(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_10, IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10, VAL << IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Pos);
}

static inline uint32_t get_irq_mask_map_control_10_irq_map_10(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_10, IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10) >> IRQ_MASK_MAP_CONTROL_10_IRQ_MAP_10_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_11 register ********************************/

static inline void set_irq_mask_map_control_11_irq_mask_11(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_11, IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11, VAL << IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Pos);
}

static inline uint32_t get_irq_mask_map_control_11_irq_mask_11(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_11, IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11) >> IRQ_MASK_MAP_CONTROL_11_IRQ_MASK_11_Pos);
}

static inline void set_irq_mask_map_control_11_irq_map_11(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_11, IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11, VAL << IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Pos);
}

static inline uint32_t get_irq_mask_map_control_11_irq_map_11(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_11, IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11) >> IRQ_MASK_MAP_CONTROL_11_IRQ_MAP_11_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_12 register ********************************/

static inline void set_irq_mask_map_control_12_irq_mask_12(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_12, IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12, VAL << IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Pos);
}

static inline uint32_t get_irq_mask_map_control_12_irq_mask_12(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_12, IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12) >> IRQ_MASK_MAP_CONTROL_12_IRQ_MASK_12_Pos);
}

static inline void set_irq_mask_map_control_12_irq_map_12(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_12, IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12, VAL << IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Pos);
}

static inline uint32_t get_irq_mask_map_control_12_irq_map_12(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_12, IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12) >> IRQ_MASK_MAP_CONTROL_12_IRQ_MAP_12_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_13 register ********************************/

static inline void set_irq_mask_map_control_13_irq_mask_13(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_13, IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13, VAL << IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Pos);
}

static inline uint32_t get_irq_mask_map_control_13_irq_mask_13(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_13, IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13) >> IRQ_MASK_MAP_CONTROL_13_IRQ_MASK_13_Pos);
}

static inline void set_irq_mask_map_control_13_irq_map_13(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_13, IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13, VAL << IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Pos);
}

static inline uint32_t get_irq_mask_map_control_13_irq_map_13(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_13, IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13) >> IRQ_MASK_MAP_CONTROL_13_IRQ_MAP_13_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_14 register ********************************/

static inline void set_irq_mask_map_control_14_irq_mask_14(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_14, IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14, VAL << IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Pos);
}

static inline uint32_t get_irq_mask_map_control_14_irq_mask_14(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_14, IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14) >> IRQ_MASK_MAP_CONTROL_14_IRQ_MASK_14_Pos);
}

static inline void set_irq_mask_map_control_14_irq_map_14(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_14, IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14, VAL << IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Pos);
}

static inline uint32_t get_irq_mask_map_control_14_irq_map_14(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_14, IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14) >> IRQ_MASK_MAP_CONTROL_14_IRQ_MAP_14_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_15 register ********************************/

static inline void set_irq_mask_map_control_15_irq_mask_15(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_15, IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15, VAL << IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Pos);
}

static inline uint32_t get_irq_mask_map_control_15_irq_mask_15(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_15, IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15) >> IRQ_MASK_MAP_CONTROL_15_IRQ_MASK_15_Pos);
}

static inline void set_irq_mask_map_control_15_irq_map_15(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_15, IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15, VAL << IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Pos);
}

static inline uint32_t get_irq_mask_map_control_15_irq_map_15(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_15, IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15) >> IRQ_MASK_MAP_CONTROL_15_IRQ_MAP_15_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_16 register ********************************/

static inline void set_irq_mask_map_control_16_irq_mask_16(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_16, IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16, VAL << IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Pos);
}

static inline uint32_t get_irq_mask_map_control_16_irq_mask_16(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_16, IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16) >> IRQ_MASK_MAP_CONTROL_16_IRQ_MASK_16_Pos);
}

static inline void set_irq_mask_map_control_16_irq_map_16(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_16, IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16, VAL << IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Pos);
}

static inline uint32_t get_irq_mask_map_control_16_irq_map_16(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_16, IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16) >> IRQ_MASK_MAP_CONTROL_16_IRQ_MAP_16_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_17 register ********************************/

static inline void set_irq_mask_map_control_17_irq_mask_17(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_17, IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17, VAL << IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Pos);
}

static inline uint32_t get_irq_mask_map_control_17_irq_mask_17(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_17, IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17) >> IRQ_MASK_MAP_CONTROL_17_IRQ_MASK_17_Pos);
}

static inline void set_irq_mask_map_control_17_irq_map_17(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_17, IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17, VAL << IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Pos);
}

static inline uint32_t get_irq_mask_map_control_17_irq_map_17(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_17, IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17) >> IRQ_MASK_MAP_CONTROL_17_IRQ_MAP_17_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_18 register ********************************/

static inline void set_irq_mask_map_control_18_irq_mask_18(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_18, IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18, VAL << IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Pos);
}

static inline uint32_t get_irq_mask_map_control_18_irq_mask_18(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_18, IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18) >> IRQ_MASK_MAP_CONTROL_18_IRQ_MASK_18_Pos);
}

static inline void set_irq_mask_map_control_18_irq_map_18(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_18, IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18, VAL << IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Pos);
}

static inline uint32_t get_irq_mask_map_control_18_irq_map_18(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_18, IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18) >> IRQ_MASK_MAP_CONTROL_18_IRQ_MAP_18_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_19 register ********************************/

static inline void set_irq_mask_map_control_19_irq_mask_19(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_19, IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19, VAL << IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Pos);
}

static inline uint32_t get_irq_mask_map_control_19_irq_mask_19(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_19, IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19) >> IRQ_MASK_MAP_CONTROL_19_IRQ_MASK_19_Pos);
}

static inline void set_irq_mask_map_control_19_irq_map_19(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_19, IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19, VAL << IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Pos);
}

static inline uint32_t get_irq_mask_map_control_19_irq_map_19(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_19, IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19) >> IRQ_MASK_MAP_CONTROL_19_IRQ_MAP_19_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_20 register ********************************/

static inline void set_irq_mask_map_control_20_irq_mask_20(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_20, IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20, VAL << IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Pos);
}

static inline uint32_t get_irq_mask_map_control_20_irq_mask_20(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_20, IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20) >> IRQ_MASK_MAP_CONTROL_20_IRQ_MASK_20_Pos);
}

static inline void set_irq_mask_map_control_20_irq_map_20(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_20, IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20, VAL << IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Pos);
}

static inline uint32_t get_irq_mask_map_control_20_irq_map_20(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_20, IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20) >> IRQ_MASK_MAP_CONTROL_20_IRQ_MAP_20_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_21 register ********************************/

static inline void set_irq_mask_map_control_21_irq_mask_21(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_21, IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21, VAL << IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Pos);
}

static inline uint32_t get_irq_mask_map_control_21_irq_mask_21(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_21, IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21) >> IRQ_MASK_MAP_CONTROL_21_IRQ_MASK_21_Pos);
}

static inline void set_irq_mask_map_control_21_irq_map_21(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_21, IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21, VAL << IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Pos);
}

static inline uint32_t get_irq_mask_map_control_21_irq_map_21(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_21, IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21) >> IRQ_MASK_MAP_CONTROL_21_IRQ_MAP_21_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_22 register ********************************/

static inline void set_irq_mask_map_control_22_irq_mask_22(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_22, IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22, VAL << IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Pos);
}

static inline uint32_t get_irq_mask_map_control_22_irq_mask_22(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_22, IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22) >> IRQ_MASK_MAP_CONTROL_22_IRQ_MASK_22_Pos);
}

static inline void set_irq_mask_map_control_22_irq_map_22(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_22, IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22, VAL << IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Pos);
}

static inline uint32_t get_irq_mask_map_control_22_irq_map_22(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_22, IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22) >> IRQ_MASK_MAP_CONTROL_22_IRQ_MAP_22_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_23 register ********************************/

static inline void set_irq_mask_map_control_23_irq_mask_23(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_23, IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23, VAL << IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Pos);
}

static inline uint32_t get_irq_mask_map_control_23_irq_mask_23(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_23, IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23) >> IRQ_MASK_MAP_CONTROL_23_IRQ_MASK_23_Pos);
}

static inline void set_irq_mask_map_control_23_irq_map_23(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_23, IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23, VAL << IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Pos);
}

static inline uint32_t get_irq_mask_map_control_23_irq_map_23(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_23, IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23) >> IRQ_MASK_MAP_CONTROL_23_IRQ_MAP_23_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_24 register ********************************/

static inline void set_irq_mask_map_control_24_irq_mask_24(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_24, IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24, VAL << IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Pos);
}

static inline uint32_t get_irq_mask_map_control_24_irq_mask_24(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_24, IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24) >> IRQ_MASK_MAP_CONTROL_24_IRQ_MASK_24_Pos);
}

static inline void set_irq_mask_map_control_24_irq_map_24(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_24, IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24, VAL << IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Pos);
}

static inline uint32_t get_irq_mask_map_control_24_irq_map_24(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_24, IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24) >> IRQ_MASK_MAP_CONTROL_24_IRQ_MAP_24_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_25 register ********************************/

static inline void set_irq_mask_map_control_25_irq_mask_25(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_25, IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25, VAL << IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Pos);
}

static inline uint32_t get_irq_mask_map_control_25_irq_mask_25(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_25, IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25) >> IRQ_MASK_MAP_CONTROL_25_IRQ_MASK_25_Pos);
}

static inline void set_irq_mask_map_control_25_irq_map_25(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_25, IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25, VAL << IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Pos);
}

static inline uint32_t get_irq_mask_map_control_25_irq_map_25(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_25, IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25) >> IRQ_MASK_MAP_CONTROL_25_IRQ_MAP_25_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_26 register ********************************/

static inline void set_irq_mask_map_control_26_irq_mask_26(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_26, IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26, VAL << IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Pos);
}

static inline uint32_t get_irq_mask_map_control_26_irq_mask_26(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_26, IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26) >> IRQ_MASK_MAP_CONTROL_26_IRQ_MASK_26_Pos);
}

static inline void set_irq_mask_map_control_26_irq_map_26(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_26, IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26, VAL << IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Pos);
}

static inline uint32_t get_irq_mask_map_control_26_irq_map_26(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_26, IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26) >> IRQ_MASK_MAP_CONTROL_26_IRQ_MAP_26_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_27 register ********************************/

static inline void set_irq_mask_map_control_27_irq_mask_27(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_27, IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27, VAL << IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Pos);
}

static inline uint32_t get_irq_mask_map_control_27_irq_mask_27(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_27, IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27) >> IRQ_MASK_MAP_CONTROL_27_IRQ_MASK_27_Pos);
}

static inline void set_irq_mask_map_control_27_irq_map_27(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_27, IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27, VAL << IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Pos);
}

static inline uint32_t get_irq_mask_map_control_27_irq_map_27(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_27, IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27) >> IRQ_MASK_MAP_CONTROL_27_IRQ_MAP_27_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_28 register ********************************/

static inline void set_irq_mask_map_control_28_irq_mask_28(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_28, IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28, VAL << IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Pos);
}

static inline uint32_t get_irq_mask_map_control_28_irq_mask_28(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_28, IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28) >> IRQ_MASK_MAP_CONTROL_28_IRQ_MASK_28_Pos);
}

static inline void set_irq_mask_map_control_28_irq_map_28(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_28, IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28, VAL << IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Pos);
}

static inline uint32_t get_irq_mask_map_control_28_irq_map_28(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_28, IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28) >> IRQ_MASK_MAP_CONTROL_28_IRQ_MAP_28_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_29 register ********************************/

static inline void set_irq_mask_map_control_29_irq_mask_29(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_29, IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29, VAL << IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Pos);
}

static inline uint32_t get_irq_mask_map_control_29_irq_mask_29(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_29, IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29) >> IRQ_MASK_MAP_CONTROL_29_IRQ_MASK_29_Pos);
}

static inline void set_irq_mask_map_control_29_irq_map_29(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_29, IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29, VAL << IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Pos);
}

static inline uint32_t get_irq_mask_map_control_29_irq_map_29(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_29, IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29) >> IRQ_MASK_MAP_CONTROL_29_IRQ_MAP_29_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_30 register ********************************/

static inline void set_irq_mask_map_control_30_irq_mask_30(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_30, IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30, VAL << IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Pos);
}

static inline uint32_t get_irq_mask_map_control_30_irq_mask_30(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_30, IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30) >> IRQ_MASK_MAP_CONTROL_30_IRQ_MASK_30_Pos);
}

static inline void set_irq_mask_map_control_30_irq_map_30(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_30, IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30, VAL << IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Pos);
}

static inline uint32_t get_irq_mask_map_control_30_irq_map_30(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_30, IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30) >> IRQ_MASK_MAP_CONTROL_30_IRQ_MAP_30_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_31 register ********************************/

static inline void set_irq_mask_map_control_31_irq_mask_31(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_31, IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31, VAL << IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Pos);
}

static inline uint32_t get_irq_mask_map_control_31_irq_mask_31(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_31, IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31) >> IRQ_MASK_MAP_CONTROL_31_IRQ_MASK_31_Pos);
}

static inline void set_irq_mask_map_control_31_irq_map_31(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_31, IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31, VAL << IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Pos);
}

static inline uint32_t get_irq_mask_map_control_31_irq_map_31(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_31, IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31) >> IRQ_MASK_MAP_CONTROL_31_IRQ_MAP_31_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_32 register ********************************/

static inline void set_irq_mask_map_control_32_irq_mask_32(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_32, IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32, VAL << IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Pos);
}

static inline uint32_t get_irq_mask_map_control_32_irq_mask_32(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_32, IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32) >> IRQ_MASK_MAP_CONTROL_32_IRQ_MASK_32_Pos);
}

static inline void set_irq_mask_map_control_32_irq_map_32(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_32, IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32, VAL << IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Pos);
}

static inline uint32_t get_irq_mask_map_control_32_irq_map_32(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_32, IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32) >> IRQ_MASK_MAP_CONTROL_32_IRQ_MAP_32_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_33 register ********************************/

static inline void set_irq_mask_map_control_33_irq_mask_33(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_33, IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33, VAL << IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Pos);
}

static inline uint32_t get_irq_mask_map_control_33_irq_mask_33(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_33, IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33) >> IRQ_MASK_MAP_CONTROL_33_IRQ_MASK_33_Pos);
}

static inline void set_irq_mask_map_control_33_irq_map_33(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_33, IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33, VAL << IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Pos);
}

static inline uint32_t get_irq_mask_map_control_33_irq_map_33(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_33, IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33) >> IRQ_MASK_MAP_CONTROL_33_IRQ_MAP_33_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_34 register ********************************/

static inline void set_irq_mask_map_control_34_irq_mask_34(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_34, IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34, VAL << IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Pos);
}

static inline uint32_t get_irq_mask_map_control_34_irq_mask_34(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_34, IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34) >> IRQ_MASK_MAP_CONTROL_34_IRQ_MASK_34_Pos);
}

static inline void set_irq_mask_map_control_34_irq_map_34(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_34, IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34, VAL << IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Pos);
}

static inline uint32_t get_irq_mask_map_control_34_irq_map_34(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_34, IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34) >> IRQ_MASK_MAP_CONTROL_34_IRQ_MAP_34_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_35 register ********************************/

static inline void set_irq_mask_map_control_35_irq_mask_35(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_35, IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35, VAL << IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Pos);
}

static inline uint32_t get_irq_mask_map_control_35_irq_mask_35(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_35, IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35) >> IRQ_MASK_MAP_CONTROL_35_IRQ_MASK_35_Pos);
}

static inline void set_irq_mask_map_control_35_irq_map_35(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_35, IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35, VAL << IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Pos);
}

static inline uint32_t get_irq_mask_map_control_35_irq_map_35(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_35, IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35) >> IRQ_MASK_MAP_CONTROL_35_IRQ_MAP_35_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_36 register ********************************/

static inline void set_irq_mask_map_control_36_irq_mask_36(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_36, IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36, VAL << IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Pos);
}

static inline uint32_t get_irq_mask_map_control_36_irq_mask_36(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_36, IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36) >> IRQ_MASK_MAP_CONTROL_36_IRQ_MASK_36_Pos);
}

static inline void set_irq_mask_map_control_36_irq_map_36(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_36, IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36, VAL << IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Pos);
}

static inline uint32_t get_irq_mask_map_control_36_irq_map_36(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_36, IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36) >> IRQ_MASK_MAP_CONTROL_36_IRQ_MAP_36_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_37 register ********************************/

static inline void set_irq_mask_map_control_37_irq_mask_37(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_37, IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37, VAL << IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Pos);
}

static inline uint32_t get_irq_mask_map_control_37_irq_mask_37(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_37, IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37) >> IRQ_MASK_MAP_CONTROL_37_IRQ_MASK_37_Pos);
}

static inline void set_irq_mask_map_control_37_irq_map_37(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_37, IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37, VAL << IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Pos);
}

static inline uint32_t get_irq_mask_map_control_37_irq_map_37(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_37, IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37) >> IRQ_MASK_MAP_CONTROL_37_IRQ_MAP_37_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_38 register ********************************/

static inline void set_irq_mask_map_control_38_irq_mask_38(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_38, IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38, VAL << IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Pos);
}

static inline uint32_t get_irq_mask_map_control_38_irq_mask_38(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_38, IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38) >> IRQ_MASK_MAP_CONTROL_38_IRQ_MASK_38_Pos);
}

static inline void set_irq_mask_map_control_38_irq_map_38(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_38, IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38, VAL << IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Pos);
}

static inline uint32_t get_irq_mask_map_control_38_irq_map_38(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_38, IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38) >> IRQ_MASK_MAP_CONTROL_38_IRQ_MAP_38_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_39 register ********************************/

static inline void set_irq_mask_map_control_39_irq_mask_39(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_39, IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39, VAL << IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Pos);
}

static inline uint32_t get_irq_mask_map_control_39_irq_mask_39(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_39, IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39) >> IRQ_MASK_MAP_CONTROL_39_IRQ_MASK_39_Pos);
}

static inline void set_irq_mask_map_control_39_irq_map_39(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_39, IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39, VAL << IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Pos);
}

static inline uint32_t get_irq_mask_map_control_39_irq_map_39(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_39, IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39) >> IRQ_MASK_MAP_CONTROL_39_IRQ_MAP_39_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_40 register ********************************/

static inline void set_irq_mask_map_control_40_irq_mask_40(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_40, IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40, VAL << IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Pos);
}

static inline uint32_t get_irq_mask_map_control_40_irq_mask_40(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_40, IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40) >> IRQ_MASK_MAP_CONTROL_40_IRQ_MASK_40_Pos);
}

static inline void set_irq_mask_map_control_40_irq_map_40(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_40, IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40, VAL << IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Pos);
}

static inline uint32_t get_irq_mask_map_control_40_irq_map_40(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_40, IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40) >> IRQ_MASK_MAP_CONTROL_40_IRQ_MAP_40_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_41 register ********************************/

static inline void set_irq_mask_map_control_41_irq_mask_41(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_41, IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41, VAL << IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Pos);
}

static inline uint32_t get_irq_mask_map_control_41_irq_mask_41(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_41, IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41) >> IRQ_MASK_MAP_CONTROL_41_IRQ_MASK_41_Pos);
}

static inline void set_irq_mask_map_control_41_irq_map_41(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_41, IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41, VAL << IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Pos);
}

static inline uint32_t get_irq_mask_map_control_41_irq_map_41(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_41, IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41) >> IRQ_MASK_MAP_CONTROL_41_IRQ_MAP_41_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_42 register ********************************/

static inline void set_irq_mask_map_control_42_irq_mask_42(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_42, IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42, VAL << IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Pos);
}

static inline uint32_t get_irq_mask_map_control_42_irq_mask_42(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_42, IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42) >> IRQ_MASK_MAP_CONTROL_42_IRQ_MASK_42_Pos);
}

static inline void set_irq_mask_map_control_42_irq_map_42(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_42, IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42, VAL << IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Pos);
}

static inline uint32_t get_irq_mask_map_control_42_irq_map_42(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_42, IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42) >> IRQ_MASK_MAP_CONTROL_42_IRQ_MAP_42_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_43 register ********************************/

static inline void set_irq_mask_map_control_43_irq_mask_43(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_43, IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43, VAL << IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Pos);
}

static inline uint32_t get_irq_mask_map_control_43_irq_mask_43(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_43, IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43) >> IRQ_MASK_MAP_CONTROL_43_IRQ_MASK_43_Pos);
}

static inline void set_irq_mask_map_control_43_irq_map_43(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_43, IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43, VAL << IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Pos);
}

static inline uint32_t get_irq_mask_map_control_43_irq_map_43(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_43, IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43) >> IRQ_MASK_MAP_CONTROL_43_IRQ_MAP_43_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_44 register ********************************/

static inline void set_irq_mask_map_control_44_irq_mask_44(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_44, IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44, VAL << IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Pos);
}

static inline uint32_t get_irq_mask_map_control_44_irq_mask_44(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_44, IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44) >> IRQ_MASK_MAP_CONTROL_44_IRQ_MASK_44_Pos);
}

static inline void set_irq_mask_map_control_44_irq_map_44(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_44, IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44, VAL << IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Pos);
}

static inline uint32_t get_irq_mask_map_control_44_irq_map_44(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_44, IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44) >> IRQ_MASK_MAP_CONTROL_44_IRQ_MAP_44_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_45 register ********************************/

static inline void set_irq_mask_map_control_45_irq_mask_45(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_45, IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45, VAL << IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Pos);
}

static inline uint32_t get_irq_mask_map_control_45_irq_mask_45(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_45, IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45) >> IRQ_MASK_MAP_CONTROL_45_IRQ_MASK_45_Pos);
}

static inline void set_irq_mask_map_control_45_irq_map_45(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_45, IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45, VAL << IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Pos);
}

static inline uint32_t get_irq_mask_map_control_45_irq_map_45(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_45, IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45) >> IRQ_MASK_MAP_CONTROL_45_IRQ_MAP_45_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_46 register ********************************/

static inline void set_irq_mask_map_control_46_irq_mask_46(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_46, IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46, VAL << IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Pos);
}

static inline uint32_t get_irq_mask_map_control_46_irq_mask_46(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_46, IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46) >> IRQ_MASK_MAP_CONTROL_46_IRQ_MASK_46_Pos);
}

static inline void set_irq_mask_map_control_46_irq_map_46(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_46, IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46, VAL << IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Pos);
}

static inline uint32_t get_irq_mask_map_control_46_irq_map_46(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_46, IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46) >> IRQ_MASK_MAP_CONTROL_46_IRQ_MAP_46_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_47 register ********************************/

static inline void set_irq_mask_map_control_47_irq_mask_47(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_47, IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47, VAL << IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Pos);
}

static inline uint32_t get_irq_mask_map_control_47_irq_mask_47(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_47, IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47) >> IRQ_MASK_MAP_CONTROL_47_IRQ_MASK_47_Pos);
}

static inline void set_irq_mask_map_control_47_irq_map_47(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_47, IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47, VAL << IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Pos);
}

static inline uint32_t get_irq_mask_map_control_47_irq_map_47(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_47, IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47) >> IRQ_MASK_MAP_CONTROL_47_IRQ_MAP_47_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_48 register ********************************/

static inline void set_irq_mask_map_control_48_irq_mask_48(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_48, IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48, VAL << IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Pos);
}

static inline uint32_t get_irq_mask_map_control_48_irq_mask_48(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_48, IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48) >> IRQ_MASK_MAP_CONTROL_48_IRQ_MASK_48_Pos);
}

static inline void set_irq_mask_map_control_48_irq_map_48(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_48, IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48, VAL << IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Pos);
}

static inline uint32_t get_irq_mask_map_control_48_irq_map_48(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_48, IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48) >> IRQ_MASK_MAP_CONTROL_48_IRQ_MAP_48_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_49 register ********************************/

static inline void set_irq_mask_map_control_49_irq_mask_49(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_49, IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49, VAL << IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Pos);
}

static inline uint32_t get_irq_mask_map_control_49_irq_mask_49(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_49, IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49) >> IRQ_MASK_MAP_CONTROL_49_IRQ_MASK_49_Pos);
}

static inline void set_irq_mask_map_control_49_irq_map_49(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_49, IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49, VAL << IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Pos);
}

static inline uint32_t get_irq_mask_map_control_49_irq_map_49(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_49, IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49) >> IRQ_MASK_MAP_CONTROL_49_IRQ_MAP_49_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_50 register ********************************/

static inline void set_irq_mask_map_control_50_irq_mask_50(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_50, IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50, VAL << IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Pos);
}

static inline uint32_t get_irq_mask_map_control_50_irq_mask_50(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_50, IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50) >> IRQ_MASK_MAP_CONTROL_50_IRQ_MASK_50_Pos);
}

static inline void set_irq_mask_map_control_50_irq_map_50(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_50, IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50, VAL << IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Pos);
}

static inline uint32_t get_irq_mask_map_control_50_irq_map_50(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_50, IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50) >> IRQ_MASK_MAP_CONTROL_50_IRQ_MAP_50_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_51 register ********************************/

static inline void set_irq_mask_map_control_51_irq_mask_51(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_51, IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51, VAL << IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Pos);
}

static inline uint32_t get_irq_mask_map_control_51_irq_mask_51(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_51, IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51) >> IRQ_MASK_MAP_CONTROL_51_IRQ_MASK_51_Pos);
}

static inline void set_irq_mask_map_control_51_irq_map_51(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_51, IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51, VAL << IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Pos);
}

static inline uint32_t get_irq_mask_map_control_51_irq_map_51(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_51, IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51) >> IRQ_MASK_MAP_CONTROL_51_IRQ_MAP_51_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_52 register ********************************/

static inline void set_irq_mask_map_control_52_irq_mask_52(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_52, IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52, VAL << IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Pos);
}

static inline uint32_t get_irq_mask_map_control_52_irq_mask_52(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_52, IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52) >> IRQ_MASK_MAP_CONTROL_52_IRQ_MASK_52_Pos);
}

static inline void set_irq_mask_map_control_52_irq_map_52(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_52, IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52, VAL << IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Pos);
}

static inline uint32_t get_irq_mask_map_control_52_irq_map_52(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_52, IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52) >> IRQ_MASK_MAP_CONTROL_52_IRQ_MAP_52_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_53 register ********************************/

static inline void set_irq_mask_map_control_53_irq_mask_53(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_53, IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53, VAL << IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Pos);
}

static inline uint32_t get_irq_mask_map_control_53_irq_mask_53(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_53, IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53) >> IRQ_MASK_MAP_CONTROL_53_IRQ_MASK_53_Pos);
}

static inline void set_irq_mask_map_control_53_irq_map_53(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_53, IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53, VAL << IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Pos);
}

static inline uint32_t get_irq_mask_map_control_53_irq_map_53(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_53, IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53) >> IRQ_MASK_MAP_CONTROL_53_IRQ_MAP_53_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_54 register ********************************/

static inline void set_irq_mask_map_control_54_irq_mask_54(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_54, IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54, VAL << IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Pos);
}

static inline uint32_t get_irq_mask_map_control_54_irq_mask_54(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_54, IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54) >> IRQ_MASK_MAP_CONTROL_54_IRQ_MASK_54_Pos);
}

static inline void set_irq_mask_map_control_54_irq_map_54(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_54, IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54, VAL << IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Pos);
}

static inline uint32_t get_irq_mask_map_control_54_irq_map_54(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_54, IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54) >> IRQ_MASK_MAP_CONTROL_54_IRQ_MAP_54_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_55 register ********************************/

static inline void set_irq_mask_map_control_55_irq_mask_55(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_55, IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55, VAL << IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Pos);
}

static inline uint32_t get_irq_mask_map_control_55_irq_mask_55(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_55, IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55) >> IRQ_MASK_MAP_CONTROL_55_IRQ_MASK_55_Pos);
}

static inline void set_irq_mask_map_control_55_irq_map_55(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_55, IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55, VAL << IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Pos);
}

static inline uint32_t get_irq_mask_map_control_55_irq_map_55(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_55, IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55) >> IRQ_MASK_MAP_CONTROL_55_IRQ_MAP_55_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_56 register ********************************/

static inline void set_irq_mask_map_control_56_irq_mask_56(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_56, IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56, VAL << IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Pos);
}

static inline uint32_t get_irq_mask_map_control_56_irq_mask_56(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_56, IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56) >> IRQ_MASK_MAP_CONTROL_56_IRQ_MASK_56_Pos);
}

static inline void set_irq_mask_map_control_56_irq_map_56(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_56, IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56, VAL << IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Pos);
}

static inline uint32_t get_irq_mask_map_control_56_irq_map_56(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_56, IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56) >> IRQ_MASK_MAP_CONTROL_56_IRQ_MAP_56_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_57 register ********************************/

static inline void set_irq_mask_map_control_57_irq_mask_57(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_57, IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57, VAL << IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Pos);
}

static inline uint32_t get_irq_mask_map_control_57_irq_mask_57(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_57, IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57) >> IRQ_MASK_MAP_CONTROL_57_IRQ_MASK_57_Pos);
}

static inline void set_irq_mask_map_control_57_irq_map_57(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_57, IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57, VAL << IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Pos);
}

static inline uint32_t get_irq_mask_map_control_57_irq_map_57(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_57, IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57) >> IRQ_MASK_MAP_CONTROL_57_IRQ_MAP_57_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_58 register ********************************/

static inline void set_irq_mask_map_control_58_irq_mask_58(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_58, IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58, VAL << IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Pos);
}

static inline uint32_t get_irq_mask_map_control_58_irq_mask_58(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_58, IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58) >> IRQ_MASK_MAP_CONTROL_58_IRQ_MASK_58_Pos);
}

static inline void set_irq_mask_map_control_58_irq_map_58(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_58, IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58, VAL << IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Pos);
}

static inline uint32_t get_irq_mask_map_control_58_irq_map_58(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_58, IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58) >> IRQ_MASK_MAP_CONTROL_58_IRQ_MAP_58_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_59 register ********************************/

static inline void set_irq_mask_map_control_59_irq_mask_59(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_59, IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59, VAL << IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Pos);
}

static inline uint32_t get_irq_mask_map_control_59_irq_mask_59(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_59, IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59) >> IRQ_MASK_MAP_CONTROL_59_IRQ_MASK_59_Pos);
}

static inline void set_irq_mask_map_control_59_irq_map_59(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_59, IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59, VAL << IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Pos);
}

static inline uint32_t get_irq_mask_map_control_59_irq_map_59(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_59, IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59) >> IRQ_MASK_MAP_CONTROL_59_IRQ_MAP_59_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_60 register ********************************/

static inline void set_irq_mask_map_control_60_irq_mask_60(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_60, IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60, VAL << IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Pos);
}

static inline uint32_t get_irq_mask_map_control_60_irq_mask_60(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_60, IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60) >> IRQ_MASK_MAP_CONTROL_60_IRQ_MASK_60_Pos);
}

static inline void set_irq_mask_map_control_60_irq_map_60(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_60, IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60, VAL << IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Pos);
}

static inline uint32_t get_irq_mask_map_control_60_irq_map_60(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_60, IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60) >> IRQ_MASK_MAP_CONTROL_60_IRQ_MAP_60_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_61 register ********************************/

static inline void set_irq_mask_map_control_61_irq_mask_61(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_61, IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61, VAL << IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Pos);
}

static inline uint32_t get_irq_mask_map_control_61_irq_mask_61(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_61, IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61) >> IRQ_MASK_MAP_CONTROL_61_IRQ_MASK_61_Pos);
}

static inline void set_irq_mask_map_control_61_irq_map_61(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_61, IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61, VAL << IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Pos);
}

static inline uint32_t get_irq_mask_map_control_61_irq_map_61(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_61, IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61) >> IRQ_MASK_MAP_CONTROL_61_IRQ_MAP_61_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_62 register ********************************/

static inline void set_irq_mask_map_control_62_irq_mask_62(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_62, IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62, VAL << IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Pos);
}

static inline uint32_t get_irq_mask_map_control_62_irq_mask_62(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_62, IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62) >> IRQ_MASK_MAP_CONTROL_62_IRQ_MASK_62_Pos);
}

static inline void set_irq_mask_map_control_62_irq_map_62(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_62, IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62, VAL << IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Pos);
}

static inline uint32_t get_irq_mask_map_control_62_irq_map_62(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_62, IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62) >> IRQ_MASK_MAP_CONTROL_62_IRQ_MAP_62_Pos);
}

/****************************** Inline function for IRQ_MASK_MAP_CONTROL_63 register ********************************/

static inline void set_irq_mask_map_control_63_irq_mask_63(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_63, IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63, VAL << IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Pos);
}

static inline uint32_t get_irq_mask_map_control_63_irq_mask_63(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_63, IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63) >> IRQ_MASK_MAP_CONTROL_63_IRQ_MASK_63_Pos);
}

static inline void set_irq_mask_map_control_63_irq_map_63(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IRQ_MASK_MAP_CONTROL_63, IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63, VAL << IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Pos);
}

static inline uint32_t get_irq_mask_map_control_63_irq_map_63(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IRQ_MASK_MAP_CONTROL_63, IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63) >> IRQ_MASK_MAP_CONTROL_63_IRQ_MAP_63_Pos);
}

/****************************** Inline function for AXI_CLK_EN_M0 register ********************************/

static inline void set_axi_clk_en_m0_axi_clk_en_m0(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->AXI_CLK_EN_M0, AXI_CLK_EN_M0_AXI_CLK_EN_M0, VAL << AXI_CLK_EN_M0_AXI_CLK_EN_M0_Pos);
}

static inline uint32_t get_axi_clk_en_m0_axi_clk_en_m0(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->AXI_CLK_EN_M0, AXI_CLK_EN_M0_AXI_CLK_EN_M0) >> AXI_CLK_EN_M0_AXI_CLK_EN_M0_Pos);
}

/****************************** Inline function for AXI_CLK_EN_M1 register ********************************/

static inline void set_axi_clk_en_m1_axi_clk_en_m1(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->AXI_CLK_EN_M1, AXI_CLK_EN_M1_AXI_CLK_EN_M1, VAL << AXI_CLK_EN_M1_AXI_CLK_EN_M1_Pos);
}

static inline uint32_t get_axi_clk_en_m1_axi_clk_en_m1(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->AXI_CLK_EN_M1, AXI_CLK_EN_M1_AXI_CLK_EN_M1) >> AXI_CLK_EN_M1_AXI_CLK_EN_M1_Pos);
}

/****************************** Inline function for AXI_CLK_EN_M2 register ********************************/

static inline void set_axi_clk_en_m2_axi_clk_en_m2(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->AXI_CLK_EN_M2, AXI_CLK_EN_M2_AXI_CLK_EN_M2, VAL << AXI_CLK_EN_M2_AXI_CLK_EN_M2_Pos);
}

static inline uint32_t get_axi_clk_en_m2_axi_clk_en_m2(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->AXI_CLK_EN_M2, AXI_CLK_EN_M2_AXI_CLK_EN_M2) >> AXI_CLK_EN_M2_AXI_CLK_EN_M2_Pos);
}

/****************************** Inline function for AXI_CLK_EN_M3 register ********************************/

static inline void set_axi_clk_en_m3_axi_clk_en_m3(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->AXI_CLK_EN_M3, AXI_CLK_EN_M3_AXI_CLK_EN_M3, VAL << AXI_CLK_EN_M3_AXI_CLK_EN_M3_Pos);
}

static inline uint32_t get_axi_clk_en_m3_axi_clk_en_m3(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->AXI_CLK_EN_M3, AXI_CLK_EN_M3_AXI_CLK_EN_M3) >> AXI_CLK_EN_M3_AXI_CLK_EN_M3_Pos);
}

/****************************** Inline function for ACPU_PM_STATUS register ********************************/

static inline void set_acpu_pm_status_standby_wfi_l3(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PM_STATUS, ACPU_PM_STATUS_STANDBY_WFI_L3, VAL << ACPU_PM_STATUS_STANDBY_WFI_L3_Pos);
}

static inline uint32_t get_acpu_pm_status_standby_wfi_l3(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PM_STATUS, ACPU_PM_STATUS_STANDBY_WFI_L3) >> ACPU_PM_STATUS_STANDBY_WFI_L3_Pos);
}

static inline void set_acpu_pm_status_standby_wfi(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ACPU_PM_STATUS, ACPU_PM_STATUS_STANDBY_WFI, VAL << ACPU_PM_STATUS_STANDBY_WFI_Pos);
}

static inline uint32_t get_acpu_pm_status_standby_wfi(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ACPU_PM_STATUS, ACPU_PM_STATUS_STANDBY_WFI) >> ACPU_PM_STATUS_STANDBY_WFI_Pos);
}

/****************************** Inline function for BOOT_SSI_XIP_EN register ********************************/

static inline void set_boot_ssi_xip_en_boot_ssi_xip_en(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOT_SSI_XIP_EN, BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN, VAL << BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Pos);
}

static inline uint32_t get_boot_ssi_xip_en_boot_ssi_xip_en(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOT_SSI_XIP_EN, BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN) >> BOOT_SSI_XIP_EN_BOOT_SSI_XIP_EN_Pos);
}

/****************************** Inline function for BOOT_SSI_STATUS register ********************************/

static inline void set_boot_ssi_status_boot_ssi_busy(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOT_SSI_STATUS, BOOT_SSI_STATUS_BOOT_SSI_BUSY, VAL << BOOT_SSI_STATUS_BOOT_SSI_BUSY_Pos);
}

static inline uint32_t get_boot_ssi_status_boot_ssi_busy(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOT_SSI_STATUS, BOOT_SSI_STATUS_BOOT_SSI_BUSY) >> BOOT_SSI_STATUS_BOOT_SSI_BUSY_Pos);
}

static inline void set_boot_ssi_status_boot_ssi_sleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->BOOT_SSI_STATUS, BOOT_SSI_STATUS_BOOT_SSI_SLEEP, VAL << BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Pos);
}

static inline uint32_t get_boot_ssi_status_boot_ssi_sleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->BOOT_SSI_STATUS, BOOT_SSI_STATUS_BOOT_SSI_SLEEP) >> BOOT_SSI_STATUS_BOOT_SSI_SLEEP_Pos);
}

/****************************** Inline function for GP_SSI_STATUS register ********************************/

static inline void set_gp_ssi_status_gp_ssi_busy(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GP_SSI_STATUS, GP_SSI_STATUS_GP_SSI_BUSY, VAL << GP_SSI_STATUS_GP_SSI_BUSY_Pos);
}

static inline uint32_t get_gp_ssi_status_gp_ssi_busy(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GP_SSI_STATUS, GP_SSI_STATUS_GP_SSI_BUSY) >> GP_SSI_STATUS_GP_SSI_BUSY_Pos);
}

static inline void set_gp_ssi_status_gp_ssi_sleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GP_SSI_STATUS, GP_SSI_STATUS_GP_SSI_SLEEP, VAL << GP_SSI_STATUS_GP_SSI_SLEEP_Pos);
}

static inline uint32_t get_gp_ssi_status_gp_ssi_sleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GP_SSI_STATUS, GP_SSI_STATUS_GP_SSI_SLEEP) >> GP_SSI_STATUS_GP_SSI_SLEEP_Pos);
}

/****************************** Inline function for I2C_STATUS register ********************************/

static inline void set_i2c_status_debug_hs(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_HS, VAL << I2C_STATUS_DEBUG_HS_Pos);
}

static inline uint32_t get_i2c_status_debug_hs(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_HS) >> I2C_STATUS_DEBUG_HS_Pos);
}

static inline void set_i2c_status_debug_wr(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_WR, VAL << I2C_STATUS_DEBUG_WR_Pos);
}

static inline uint32_t get_i2c_status_debug_wr(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_WR) >> I2C_STATUS_DEBUG_WR_Pos);
}

static inline void set_i2c_status_debug_rd(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_RD, VAL << I2C_STATUS_DEBUG_RD_Pos);
}

static inline uint32_t get_i2c_status_debug_rd(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_RD) >> I2C_STATUS_DEBUG_RD_Pos);
}

static inline void set_i2c_status_debug_addr(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_ADDR, VAL << I2C_STATUS_DEBUG_ADDR_Pos);
}

static inline uint32_t get_i2c_status_debug_addr(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_ADDR) >> I2C_STATUS_DEBUG_ADDR_Pos);
}

static inline void set_i2c_status_debug_data(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_DATA, VAL << I2C_STATUS_DEBUG_DATA_Pos);
}

static inline uint32_t get_i2c_status_debug_data(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_DATA) >> I2C_STATUS_DEBUG_DATA_Pos);
}

static inline void set_i2c_status_debug_p_gen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_P_GEN, VAL << I2C_STATUS_DEBUG_P_GEN_Pos);
}

static inline uint32_t get_i2c_status_debug_p_gen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_P_GEN) >> I2C_STATUS_DEBUG_P_GEN_Pos);
}

static inline void set_i2c_status_debug_s_gen(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_S_GEN, VAL << I2C_STATUS_DEBUG_S_GEN_Pos);
}

static inline uint32_t get_i2c_status_debug_s_gen(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_S_GEN) >> I2C_STATUS_DEBUG_S_GEN_Pos);
}

static inline void set_i2c_status_degub_slv_cstate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEGUB_SLV_CSTATE, VAL << I2C_STATUS_DEGUB_SLV_CSTATE_Pos);
}

static inline uint32_t get_i2c_status_degub_slv_cstate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEGUB_SLV_CSTATE) >> I2C_STATUS_DEGUB_SLV_CSTATE_Pos);
}

static inline void set_i2c_status_degub_mst_cstate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEGUB_MST_CSTATE, VAL << I2C_STATUS_DEGUB_MST_CSTATE_Pos);
}

static inline uint32_t get_i2c_status_degub_mst_cstate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEGUB_MST_CSTATE) >> I2C_STATUS_DEGUB_MST_CSTATE_Pos);
}

static inline void set_i2c_status_debug_addr_10bit(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_ADDR_10BIT, VAL << I2C_STATUS_DEBUG_ADDR_10BIT_Pos);
}

static inline uint32_t get_i2c_status_debug_addr_10bit(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_ADDR_10BIT) >> I2C_STATUS_DEBUG_ADDR_10BIT_Pos);
}

static inline void set_i2c_status_debug_slave_act(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_SLAVE_ACT, VAL << I2C_STATUS_DEBUG_SLAVE_ACT_Pos);
}

static inline uint32_t get_i2c_status_debug_slave_act(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_SLAVE_ACT) >> I2C_STATUS_DEBUG_SLAVE_ACT_Pos);
}

static inline void set_i2c_status_debug_master_act(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_DEBUG_MASTER_ACT, VAL << I2C_STATUS_DEBUG_MASTER_ACT_Pos);
}

static inline uint32_t get_i2c_status_debug_master_act(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_DEBUG_MASTER_ACT) >> I2C_STATUS_DEBUG_MASTER_ACT_Pos);
}

static inline void set_i2c_status_ic_en(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_IC_EN, VAL << I2C_STATUS_IC_EN_Pos);
}

static inline uint32_t get_i2c_status_ic_en(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_IC_EN) >> I2C_STATUS_IC_EN_Pos);
}

static inline void set_i2c_status_ic_current_src_en(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->I2C_STATUS, I2C_STATUS_IC_CURRENT_SRC_EN, VAL << I2C_STATUS_IC_CURRENT_SRC_EN_Pos);
}

static inline uint32_t get_i2c_status_ic_current_src_en(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->I2C_STATUS, I2C_STATUS_IC_CURRENT_SRC_EN) >> I2C_STATUS_IC_CURRENT_SRC_EN_Pos);
}

/****************************** Inline function for WDT_MCPU_SPEED_UP register ********************************/

static inline void set_wdt_mcpu_speed_up_wdt_mcpu_speed_up(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->WDT_MCPU_SPEED_UP, WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP, VAL << WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Pos);
}

static inline uint32_t get_wdt_mcpu_speed_up_wdt_mcpu_speed_up(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->WDT_MCPU_SPEED_UP, WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP) >> WDT_MCPU_SPEED_UP_WDT_MCPU_SPEED_UP_Pos);
}

/****************************** Inline function for GBE0_PWR_CTRL register ********************************/

static inline void set_gbe0_pwr_ctrl_gbe0_pwr_ctrl(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GBE0_PWR_CTRL, GBE0_PWR_CTRL_GBE0_PWR_CTRL, VAL << GBE0_PWR_CTRL_GBE0_PWR_CTRL_Pos);
}

static inline uint32_t get_gbe0_pwr_ctrl_gbe0_pwr_ctrl(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GBE0_PWR_CTRL, GBE0_PWR_CTRL_GBE0_PWR_CTRL) >> GBE0_PWR_CTRL_GBE0_PWR_CTRL_Pos);
}

/****************************** Inline function for GBE1_PWR_CTRL register ********************************/

static inline void set_gbe1_pwr_ctrl_gbe1_pwr_ctrl(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->GBE1_PWR_CTRL, GBE1_PWR_CTRL_GBE1_PWR_CTRL, VAL << GBE1_PWR_CTRL_GBE1_PWR_CTRL_Pos);
}

static inline uint32_t get_gbe1_pwr_ctrl_gbe1_pwr_ctrl(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->GBE1_PWR_CTRL, GBE1_PWR_CTRL_GBE1_PWR_CTRL) >> GBE1_PWR_CTRL_GBE1_PWR_CTRL_Pos);
}

/****************************** Inline function for MCPU_L2_SRAM_DEEPSLEEP register ********************************/

static inline void set_mcpu_l2_sram_deepsleep_mcpu_l2_sram_deepsleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_L2_SRAM_DEEPSLEEP, MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP, VAL << MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Pos);
}

static inline uint32_t get_mcpu_l2_sram_deepsleep_mcpu_l2_sram_deepsleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_L2_SRAM_DEEPSLEEP, MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP) >> MCPU_L2_SRAM_DEEPSLEEP_MCPU_L2_SRAM_DEEPSLEEP_Pos);
}

/****************************** Inline function for MCPU_L2_SRAM_POWERGATE register ********************************/

static inline void set_mcpu_l2_sram_powergate_mcpu_l2_sram_powergate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_L2_SRAM_POWERGATE, MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE, VAL << MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Pos);
}

static inline uint32_t get_mcpu_l2_sram_powergate_mcpu_l2_sram_powergate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_L2_SRAM_POWERGATE, MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE) >> MCPU_L2_SRAM_POWERGATE_MCPU_L2_SRAM_POWERGATE_Pos);
}

/****************************** Inline function for MCPU_HARTID register ********************************/

static inline void set_mcpu_hartid_mcpu_hartid(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_HARTID, MCPU_HARTID_MCPU_HARTID, VAL << MCPU_HARTID_MCPU_HARTID_Pos);
}

static inline uint32_t get_mcpu_hartid_mcpu_hartid(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_HARTID, MCPU_HARTID_MCPU_HARTID) >> MCPU_HARTID_MCPU_HARTID_Pos);
}

/****************************** Inline function for MCPU_IO_BASE_ADDR register ********************************/

static inline void set_mcpu_io_base_addr_mcpu_io_base_addr(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_IO_BASE_ADDR, MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR, VAL << MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Pos);
}

static inline uint32_t get_mcpu_io_base_addr_mcpu_io_base_addr(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_IO_BASE_ADDR, MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR) >> MCPU_IO_BASE_ADDR_MCPU_IO_BASE_ADDR_Pos);
}

/****************************** Inline function for MCPU_MEM_BASE_ADDR register ********************************/

static inline void set_mcpu_mem_base_addr_mcpu_mem_base_addr(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_MEM_BASE_ADDR, MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR, VAL << MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Pos);
}

static inline uint32_t get_mcpu_mem_base_addr_mcpu_mem_base_addr(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_MEM_BASE_ADDR, MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR) >> MCPU_MEM_BASE_ADDR_MCPU_MEM_BASE_ADDR_Pos);
}

/****************************** Inline function for MCPU_ICG_DIS register ********************************/

static inline void set_mcpu_icg_dis_mcpu_icg_dis(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_ICG_DIS, MCPU_ICG_DIS_MCPU_ICG_DIS, VAL << MCPU_ICG_DIS_MCPU_ICG_DIS_Pos);
}

static inline uint32_t get_mcpu_icg_dis_mcpu_icg_dis(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_ICG_DIS, MCPU_ICG_DIS_MCPU_ICG_DIS) >> MCPU_ICG_DIS_MCPU_ICG_DIS_Pos);
}

/****************************** Inline function for MCPU_CLK_DIS register ********************************/

static inline void set_mcpu_clk_dis_mcpu_clk_dis(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_CLK_DIS, MCPU_CLK_DIS_MCPU_CLK_DIS, VAL << MCPU_CLK_DIS_MCPU_CLK_DIS_Pos);
}

static inline uint32_t get_mcpu_clk_dis_mcpu_clk_dis(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_CLK_DIS, MCPU_CLK_DIS_MCPU_CLK_DIS) >> MCPU_CLK_DIS_MCPU_CLK_DIS_Pos);
}

/****************************** Inline function for MCPU_RST_CORE_PC register ********************************/

static inline void set_mcpu_rst_core_pc_mcpu_rst_core_pc(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCPU_RST_CORE_PC, MCPU_RST_CORE_PC_MCPU_RST_CORE_PC, VAL << MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Pos);
}

static inline uint32_t get_mcpu_rst_core_pc_mcpu_rst_core_pc(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCPU_RST_CORE_PC, MCPU_RST_CORE_PC_MCPU_RST_CORE_PC) >> MCPU_RST_CORE_PC_MCPU_RST_CORE_PC_Pos);
}

/****************************** Inline function for DTCM_DEEPSLEEP register ********************************/

static inline void set_dtcm_deepsleep_dtcm_deepsleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DTCM_DEEPSLEEP, DTCM_DEEPSLEEP_DTCM_DEEPSLEEP, VAL << DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Pos);
}

static inline uint32_t get_dtcm_deepsleep_dtcm_deepsleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DTCM_DEEPSLEEP, DTCM_DEEPSLEEP_DTCM_DEEPSLEEP) >> DTCM_DEEPSLEEP_DTCM_DEEPSLEEP_Pos);
}

/****************************** Inline function for DTCM_POWERGATE register ********************************/

static inline void set_dtcm_powergate_dtcm_powergate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DTCM_POWERGATE, DTCM_POWERGATE_DTCM_POWERGATE, VAL << DTCM_POWERGATE_DTCM_POWERGATE_Pos);
}

static inline uint32_t get_dtcm_powergate_dtcm_powergate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DTCM_POWERGATE, DTCM_POWERGATE_DTCM_POWERGATE) >> DTCM_POWERGATE_DTCM_POWERGATE_Pos);
}

/****************************** Inline function for ITCM_DEEPSLEEP register ********************************/

static inline void set_itcm_deepsleep_itcm_deepsleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ITCM_DEEPSLEEP, ITCM_DEEPSLEEP_ITCM_DEEPSLEEP, VAL << ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Pos);
}

static inline uint32_t get_itcm_deepsleep_itcm_deepsleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ITCM_DEEPSLEEP, ITCM_DEEPSLEEP_ITCM_DEEPSLEEP) >> ITCM_DEEPSLEEP_ITCM_DEEPSLEEP_Pos);
}

/****************************** Inline function for ITCM_POWERGATE register ********************************/

static inline void set_itcm_powergate_itcm_powergate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->ITCM_POWERGATE, ITCM_POWERGATE_ITCM_POWERGATE, VAL << ITCM_POWERGATE_ITCM_POWERGATE_Pos);
}

static inline uint32_t get_itcm_powergate_itcm_powergate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->ITCM_POWERGATE, ITCM_POWERGATE_ITCM_POWERGATE) >> ITCM_POWERGATE_ITCM_POWERGATE_Pos);
}

/****************************** Inline function for MISC_DEEPSLEEP register ********************************/

static inline void set_misc_deepsleep_misc_deepsleep(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MISC_DEEPSLEEP, MISC_DEEPSLEEP_MISC_DEEPSLEEP, VAL << MISC_DEEPSLEEP_MISC_DEEPSLEEP_Pos);
}

static inline uint32_t get_misc_deepsleep_misc_deepsleep(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MISC_DEEPSLEEP, MISC_DEEPSLEEP_MISC_DEEPSLEEP) >> MISC_DEEPSLEEP_MISC_DEEPSLEEP_Pos);
}

/****************************** Inline function for MISC_POWERGATE register ********************************/

static inline void set_misc_powergate_misc_powergate(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MISC_POWERGATE, MISC_POWERGATE_MISC_POWERGATE, VAL << MISC_POWERGATE_MISC_POWERGATE_Pos);
}

static inline uint32_t get_misc_powergate_misc_powergate(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MISC_POWERGATE, MISC_POWERGATE_MISC_POWERGATE) >> MISC_POWERGATE_MISC_POWERGATE_Pos);
}

/****************************** Inline function for JTAG_SEL register ********************************/

static inline void set_jtag_sel_jtag_sel(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->JTAG_SEL, JTAG_SEL_JTAG_SEL, VAL << JTAG_SEL_JTAG_SEL_Pos);
}

static inline uint32_t get_jtag_sel_jtag_sel(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->JTAG_SEL, JTAG_SEL_JTAG_SEL) >> JTAG_SEL_JTAG_SEL_Pos);
}

static inline void set_jtag_sel_acpu_jtag_sel_core(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->JTAG_SEL, JTAG_SEL_ACPU_JTAG_SEL_CORE, VAL << JTAG_SEL_ACPU_JTAG_SEL_CORE_Pos);
}

static inline uint32_t get_jtag_sel_acpu_jtag_sel_core(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->JTAG_SEL, JTAG_SEL_ACPU_JTAG_SEL_CORE) >> JTAG_SEL_ACPU_JTAG_SEL_CORE_Pos);
}

/****************************** Inline function for EXT_ADDR register ********************************/

static inline void set_ext_addr_ext_addr(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->EXT_ADDR, EXT_ADDR_EXT_ADDR, VAL << EXT_ADDR_EXT_ADDR_Pos);
}

static inline uint32_t get_ext_addr_ext_addr(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->EXT_ADDR, EXT_ADDR_EXT_ADDR) >> EXT_ADDR_EXT_ADDR_Pos);
}

/****************************** Inline function for SW_RST_N_MCPU register ********************************/

static inline void set_sw_rst_n_mcpu_sw_rst_n_mcpu(SCU_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SW_RST_N_MCPU, SW_RST_N_MCPU_SW_RST_N_MCPU, VAL << SW_RST_N_MCPU_SW_RST_N_MCPU_Pos);
}

static inline uint32_t get_sw_rst_n_mcpu_sw_rst_n_mcpu(SCU_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SW_RST_N_MCPU, SW_RST_N_MCPU_SW_RST_N_MCPU) >> SW_RST_N_MCPU_SW_RST_N_MCPU_Pos);
}

void scu_init(SCU_t *SCU);

#endif // __SCU_H__
